VHDL(5)

💅 NAME 💅

ALLIANCE VHDL Subset — this is VHDL(5), section 5 of the manual, and bestie, it's the whole vibe check on what VHDL you're actually allowed to write in this house. 🫶

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🌸 ORIGIN 🌸

Okay so this software belongs to the ALLIANCE CAD SYSTEM, which was developed by the ASIM team at the LIP6 laboratory of Université Pierre et Marie CURIE, in Paris, France. 🥐✨

• Web: http://asim.lip6.fr/recherche/alliance/
• E-mail: alliance-users@asim.lip6.fr

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✨ DESCRIPTION ✨

The ALLIANCE VHDL subset is dedicated to digital synchronous circuits design, periodt. And the same subset is used for all of these:

• logic simulation (asimut)
• logic synthesis (boom, boog, loon)
• functional abstraction (yagle)
• formal proof (proof)

The ALLIANCE VHDL subset is fully compatible with the IEEE VHDL standard Ref. 1076 (1987). Which means — and this is the iconic part — a VHDL description using the ALLIANCE subset can be simulated with any full-VHDL commercial compiler-simulator. No cap. 💅

Here follows the main restrictions of the ALLIANCE subset. Buckle up. 🎀

🦋 External view vs internal view

The VHDL description of a circuit is made of two separate parts: the external view and the internal view.

The external view defines the name of the circuit and its interface. The interface of a circuit is a list of ports. Each port is specified by:

• its name
• its mode
• its type
• its constraint for an array
• its kind

The mode of a port depends only on the manner the port is used inside the circuit (in the internal view of the circuit):

• if the value of a port is to be read in the view of the description → declare it with the mode in
• if the value of a port is to be written by the internal view → declare it with the mode out
• if both of the above conditions are satisfied → declare it with the mode inout

Only structural and behavioural data flow are supported as internal view.

🌈 Don't mix your vibes (structurally speaking)

In order to allow automatic translation from structural VHDL to other netlist formats (EDIF, ALLIANCE, COMPASS, ...), it is not possible to mix behavioural and structural description. That's the rule, bestie. 😤

Of course, a circuit, a subcircuit or a cell can have two different descriptions:

• a structural view may be defined in a file with a .vst extension (see vst(5))
• a behavioural data flow description may be defined in a file with a .vbe extension (see vbe(5))

A typical VHDL model will be made of a hierarchical structural description (a hierarchy of structural files) and, for each leaf cell, a behavioural description. It's giving tree structure, honestly. 🌳

🧚 Concurrent statements only, sorry

In a behavioural description, only concurrent statements (except process) are supported. Up to now, sequential statements are not allowed by the ALLIANCE VHDL compiler. 😭

⏱️ After clauses

Timing information can be specified in behavioural descriptions using After clauses. However, those delays are currently only used for simulation. After clauses are supported but not used for synthesis and formal proof.

Lowkey important: if you were counting on your After delays to mean something during synthesis or formal proof — they don't. Simulation only, babe. 💀

👑 The predefined types (user defined types? not supported, sorry)

A predefined set of types has been defined — other user defined types are not supported:

• bit — the predefined standard bit type ('0' or '1')
• bit_vector — array of bit
• mux_bit — a resolved subtype of bit using the mux resolution function. This function checks that only one driver is actually connected to a signal. The effective value of the signal is the value of the active driver. If all drivers are disconnected, the value of the signal is '1' (pull up). A signal of type mux_bit must be declared with the kind bus.
• mux_vector — array of mux_bit
• wor_bit — a resolved subtype of bit using the wor resolution function. This function allows a signal be driven by more than one driver. All active drivers have to drive the same value. The effective value of the signal is the value of active drivers. If all drivers are disconnected, the value of the signal is '1' (pull up). A signal of type wor_bit must be declared with the kind bus.
• wor_vector — array of wor_bit
• reg_bit — a resolved subtype of bit using the reg resolution function. This function checks that only one driver is actually connected to a signal. The effective value of the signal is the value of the active driver. A signal of type reg_bit must be declared with the kind register (which makes the signal keep its previous value when all drivers are disconnected).
• reg_vector — array of reg_bit

Not me reminding you again: mux_bit and wor_bit → kind bus. reg_bit → kind register. Get it wrong and the compiler will simply not be your friend. 🫠

🔮 Coming soon (in the next ALLIANCE release)

In the next ALLIANCE release the VHDL subset will be largely extended: sequential statements, user defined types. So hold onto your wig. 💖

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🎀 SEE ALSO 🎀

vst(5), vbe(5), asimut(1), boom(1), loon(1), boog(1), proof(1)

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💀 BUG REPORT 💀

This tool is under development at the ASIM department of the LIP6 laboratory.

We need your feedback to improve documentation and tools. Fr fr — tell them what's broken, they're literally asking. 🫶

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And that's a wrap on VHDL(5), brought to you by ASIM/LIP6, dated October 1, 1997. Yeah she's an elder but she ATE and left no crumbs. Stay compatible with Ref. 1076 (1987), stay concurrent, and slay. ✨🦋💜