BOOG(1)

✨ BooG(1) — the CAO-VLSI Reference Manual page, bestie edition ✨

okay so sit down, grab a lil snack 🍓, because we're talking about BooG from the CAO-VLSI Reference Manual, and she is iconic.

💖 NAME 💖

BooG — Binding and Optimizing On Gates. that's the whole name. slay.

🌈 ORIGIN 🌈

ok so this software belongs to the ALLIANCE CAD SYSTEM, developed by the ASIM team at the LIP6 laboratory of Université Pierre et Marie CURIE, in Paris, France 🇫🇷. like, literally Paris. main character energy.

• Web : http://asim.lip6.fr/recherche/alliance/
• E-mail : alliance-users@asim.lip6.fr

🦋 SYNOPSIS 🦋

boog  [-hmxold] input_file output_file  [lax_file]

💅 DESCRIPTION 💅

so boog is a mapper — she takes a behavioural description and maps it onto a predefined standard cell library like SXLIB. she's the second step of the logic synthesis, and what she does is build a gate network using a standard cell library. periodt. 👑

🌸 Input file description 🌸

the logic level behavioural description (the .vbe file) uses the same VHDL subset as the logic simulator asimut, the FSM synthesizer syf, the functional abstractor yagle and the formal prover proof (for further information about the subset of VHDL, see the vbe manual, iykyk).

some constraints due to hardware mapping exist, bestie. these attributes are only supported by technology mapping onto a standard cell library as sxlib.

for the register signal description, only one condition statement must appear. STABLE must be strictely used as a negativ motion and joined to clock setup value. setup can be on high or low value, but it would be worthy to choose it accordingly with hardware register cell. ngl that's a mouthful but it matters 💀

# Example
        label: BLOCK (NOT ck 'STABLE and ck='1')
        BEGIN
            reg <= GUARDED expr;
        END BLOCK;

you can also put a write enable condition to your register, queen:

        label: BLOCK (NOT ck 'STABLE and ck='1' and wen='1')
        BEGIN
            reg <= GUARDED expr;
        END BLOCK;

a special feature has been introduced in the VHDL subset in order to allow the don't care description for external outputs and internal registers : a bit signal can take the 'd' value 🎀. this value is interpreted as a '0' by the logic simulator asimut. Don't Cares are automatically generated by syf in the resulting .vbe file. so convenient fr fr.

🎀 Output file description 🎀

a pure standard cell netlist is produced by boog. this file is destinated for /fBloon/fP alliance utility to improve RC delays ⚡. any equipotential keeps its name from connector to connector — she does not lose names, ever. in trouble case, buffers are inserted to respect this VHDL constraint. lowkey heroic.

🧚 lax Parameter file description 🧚

the lax file is common with other logic synthesis tools and is used for driving the synthesis process. see lax(5) manual for more detail.

lax uses a lot of parameters to guide every step of the synthesis process. some parameters are globally used (for example, optimization level, whereas others are specifically used (load capacitance for the netlist optimization only)). here's the default lax file (see the user's manual for further information about the syntax of the .lax file):

   Optimization mode = 2 (50% area - 50% delay)
   Input impedance = 0
   Output capacitance = 0
   Delayed input = none
   Auxiliary signal saved = none

💜 Mapping with a standard cell library 💜

every cell appearing in the directory defined by the environment variable MBK_TARGET_LIB may be used by boog since they are described as a .vbe file. there are some restrictions about the type of the cell used, though 🙈 :

• every cell has to have only one output.
• the cell must be characterized.
• the timing and area information required by boog are specified in the "generic" clause of the .vbe file.

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✨ OPTION ✨

• -h — Help mode. Displays possible uses of boog. shoutout to -h, the friendliest flag 🫶
• -m optim_mode — Optimization mode. can be defined in lax file, it's only a shortcut to define it on command line. this mode number has an array defined between 0 and 4. it indicates the way of optimization the user wants. if 0 is chosen, the circuit area will be improved. on the other hand, 4 will improve circuit delays. 2 is a medium value for optimization. balance, queen 💅
• -x xsch_mode — Generate a .xsc file. it's a color map for each signals contained in output_file network 🎨. this file is used by xsch to view the netlist. by choosing level 0 or 1 for xsch_mode, you can color respectively the critical path or all signals with delay graduation. cute and functional.
• -o output_file — Just another way to show explicitly the VST output file name.
• -l lax_file — Just another way to show explicitly the LAX parameter file name.
• -d debug_file — Generates a VBEdebug file. it comes from internal result algorithm. users aren't concerned 🚫 (so don't worry about it, bestie).

🌟 ENVIRONMENT VARIABLES 🌟

the following environment variables have to be set before using boog :

• MBK_CATA_LIB — gives the auxiliary paths of the directories of input files (behavioural description).
• MBK_TARGET_LIB — gives the path (single) of the directory of the selected standard cell library.
• MBK_OUT_LO — gives the output format of the structural description.

like, actually set them. all three. before you run her. no cap. 😭

🔥 EXAMPLE 🔥

you can call boog as follows :

     boog alu alu

that's it. that's the whole example. she's simple like that ⭐

🦋 SEE ALSO 🦋

boog(1), boom(1), loon(1), lax(5), vbe(5), proof(1), asimut(1), vhdl(5), ocp(1), nero(1), sxlib(5).

the whole friend group, honestly 👯‍♀️

💀 BUG REPORT 💀

this tool is under development at the ASIM department of the LIP6 laboratory. we need your feedback to improve documentation and tools. so like… tell them stuff, bestie, they're literally asking 🙏

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and that's the page! 🌸 brought to you by ASIM/LIP6, dated Jun 29 2000, filed under BOOG(1) — go forth and map those gates, you gorgeous genius 🎀✨