VST(5)

💅 NAME 💅

okay so bestie, this is VST(5) — the manual page for the VHDL structural subset from the ASIM/LIP6/CAO-VLSI lab. That's the whole vibe: structural VHDL, ALLIANCE edition. 💖

🦋 ORIGIN 🦋

This software belongs to the ALLIANCE CAD SYSTEM, developed by the ASIM team at the LIP6 laboratory of Université Pierre and Marie CURIE, in Paris, France. Slay, academia. 🎀

• Web: http://asim.lip6.fr/recherche/alliance/
• E-mail: alliance-users@asim.lip6.fr

✨ DESCRIPTION ✨

This document describes the ALLIANCE VHDL subset for structural descriptions. Literally the whole point. 🫶

The declaration part of a structural description includes signal declarations and component declarations.

• An internal signal can be declared of any type supported by the present VHDL subset except reg_bit and reg_vector. Not those two, bestie. 🙈
• A component must be declared with exactly the same port description as in its entity specification. That means local ports are to be declared with the same name, type, and kind, and in the same order. No chaotic reordering. 💅

A structural description is a set of component instantiation statements. Instances' ports are connected to each other through signals in a port map specification. Both explicit and implicit port map specifications are supported by the ALLIANCE VHDL subset. Iconic. ✨

warning bestie: the present version of the VHDL compiler does not allow unconnected ports — the open mode is not supported. 🚨

Only the concatenation operator (&) can be used in the actual part (the effective signal connected to a formal port) of a port map specification. That's the rule, no cap. 🔥

💖 EXAMPLES 💖

Here's the description of an adder with an accumulator register. It's giving structural main character energy. 👑

entity add_accu is
port (
  clk      : in  bit;
  command  : in  bit;
  data_in  : in  bit_vector (31 downto 0);
  data_out : out bit_vector (31 downto 0);
  cry_out  : out bit;
  vdd      : in  bit;
  vss      : in  bit
  );
end add_accu;

architecture structural of add_accu is

signal eff_data  : bit_vector (31 downto 0);      -- effective operande
signal adder_out : bit_vector (31 downto 0);      -- adder's result
signal accu_out  : bit_vector (31 downto 0);      -- accumulator

component adder
port (a   : in  bit_vector (31 downto 0);
      b   : in  bit_vector (31 downto 0);
      res : out bit_vector (31 downto 0));
end component;

component and_32
port (a   : in  bit_vector (31 downto 0);
      cmd : in  bit;
      res : out bit_vector (31 downto 0));
end component;

component falling_edge_reg
port (din  : in  bit_vector (31 downto 0);
      clk  : in  bit;
      dout : out bit_vector (31 downto 0));
end component;

begin

  my_adder : adder
  port map (a => eff_data, b => accu_out, res => adder_out);

  my_mux   : and_32
  port map (cmd => command, a => accu_out, res => eff_data);

  my_reg   : falling_edge_reg
  port map (din => adder_out, clk => clk, dout => accu_out);

end;

🔥 SEE ALSO 🔥

• vhdl(5)
• vbe(5)
• asimut(1)

💀 BUG REPORT 💀

This tool is under development at the ASIM department of the LIP6 laboratory. We need your feedback to improve documentation and tools. Fr fr, tell them. 🫶

kisses bestie — this page is from ASIM/LIP6, dated October 1, 1997, and it's manual page VST(5). 💖🦋✨