ASIMUT(1)

💅 ASIMUT(1) — the asimut glow-up 🦋

okay bestie, so this is asimut, and it lives in the cao-vlsi reference manual — that's the manual name, you're welcome 💖

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🌸 NAME 🌸

asimut — a simulation tool for hardware descriptions. literally what it says on the tin, no cap ✨

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🎀 ORIGIN 🎀

okay so this software belongs to the ALLIANCE CAD SYSTEM, developed by the ASIM team at the LIP6 laboratory of Université Pierre et Marie CURIE, in Paris, France 👑 (the original text has a little encoding wobble in "Universit�" but you know the vibe, it's Université, fr fr).

• Web : http://asim.lip6.fr/recherche/alliance/
• E-mail : alliance-users@asim.lip6.fr

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⭐ SYNOPSIS ⭐

asimut [options] [root_file] [pattern_file] [result_file]

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🦋 DESCRIPTION 🦋

so asimut is a logical simulation tool for hardware descriptions. it compiles and loads a complete hardware description written in VHDL (Very high speed integrated circuits Hardware Description Language). the description can be structural (a hierarchy of instances) or behavioural. only a subset of VHDL is supported though — descriptions that don't match this subset throw a syntax error during compilation, so like, vibe check your VHDL first 💀. see vhdl(5) for the detailed tea on the supported subset.

once the hardware description is loaded, asimut goes looking for a simulation pattern description file. this file has to be written in pat format. it gets compiled, loaded, and linked with the hardware description, and then — we go 🏁 the simulation starts. when the patterns are processed, a result file in pat format comes out the other end. slay.

if a save action was requested in the pattern description file (peep pat (5)), asimut also creates a save file representing the state of the description at the end of the simulation of the last pattern. that save file is named root_file.sav, where root_file is the name of the description. iconic.

and the save file can be reused in a later simulation sequence to initialize the state of the (same) hardware description before the simulation begins. using this mechanism, a large sequence of patterns can be breaked onto several small sequences — each one initializing the hardware description with the save file that came out of the previous sequence. (yes, the original says "breaked", we keep the facts, we don't fix the grammar, we're just here vibing 💅)

asimut reads several parameters from the environment variables — pay attention bestie, there's a lot:

• MBK_CATA_LIB — list of directories containing description and pattern files (using $PATH syntax). the default path is the current directory (see mbk(1)).
• MBK_WORK_LIB — specifies the current working directory. the working directory is where all output files get written.
• MBK_CATAL_NAME — indicates the file where the behavioural description files are listed. this file is used to leaf cells of a structural description. (see mbk(1))
• MBK_IN_LO — file extension for structural entity. (see mbk(1))
• VH_BEHSFX — list of file extensions for behavioural entities (using $PATH syntax). the default file extension is vbe.
• VH_PATSFX — list of file extensions for pattern description entities (using $PATH syntax). the default file extension is pat.
• VH_DLYSFX — list of file extensions for delays description entities (using $PATH syntax). the default file extension is dly.
• VH_MAXERR — maximum number of errors allowed during the simulation phase. if the number of errors that occurred during simulation reaches VH_MAXERR, asimut stops the simulation at the end of processing the current pattern. the patterns following the current pattern remain unprocessed and are reproduced in the result file. the default value of VH_MAXERR is 10.

root_file is the name of the description.

by default asimut looks for a structural description. it uses the MBK_IN_LO environment variable to identify both the format and the extension of structural description files. to load structural VHDL files, MBK_IN_LO must be set to vst — no negotiash 🫶.

to load a pure behavioural description, the -b option must be specified. in that case asimut loads a data flow VHDL description file. the VH_BEHSFX environment variable gives the extensions to be used.

pattern_file is the entity name of the pattern description. the file containing this entity must be named pattern_file.ext, where ext is one of the extensions specified in VH_PATSFX.

result_file is the result file produced by asimut. the result file is a pattern description file with the extension specified by VH_PATSFX.

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✨ OPTIONS ✨

okay, the moment you've been waiting for, the full menu 🎀 every single one, no skips:

• -b — consider the root_file description as a behavioural description.
• -backdelay [min, max, typ] delay_file — use file delay_file.ext for delays backannotation, where ext is one of the extensions specified in VH_DLYSFX.
• -bdd — use BDDs (Binary Decision Diagram) to represent expressions. using this option makes the simulation be two times faster but increases memory requirement 🔥 (speed vs. RAM, the eternal struggle).
• -c — run only the compilation stage. that's it, that's the whole stage.
• -core core_file — at the first error encountered, dump the state of the circuit in both an ascii file (suffixed .cor) and a binary save file (suffixed .sav) which can be used as an initialization file in a further session. if the -nores option is specified, a pattern file is also produced. (love a good post-crash souvenir 😭)
• -dbg[sbpldc] — call the debugger (developer usage). iykyk 👀
• -defaultdelay (-dd) — only null delays (no after clause in the VHDL file) are changed if backannotated delays or fixed delays are specified.
• -fixeddelay value (-fd value) — all delays of the description are fixed to value.
• -h — display this help file. hiiii 👋
• -i value — initialize all signals of the description with value. value can be 0 or 1.
• -i save_file — read a save file and use it to initialize the state of the description before processing the first pattern. the file name cannot be 1 nor 0 ⚠️ (that would be ambiguous with the previous one, so like, don't).
• -inspect instance_name — produce a pattern file corresponding to the interface of the instance identified by instance_name.
• -l n — print at most n characters for pattern labels. the default value for n is 15.
• -nores — do not generate result file.
• -p n — load at most n patterns from the input pattern file each time. using this feature reduces memory allocation when a great number of patterns are to be simulated. in addition, after the n patterns have been processed, the simulation result is printed in the result pattern file. the default value for n is 0, which makes the whole pattern file be loaded.
• -t — trace signals when making BDDs (developer usage).
• -transport — use transport delay model (default is inertial).
• -zerodelay (-zd) — all the delays of the VHDL description are supposed to be null delays.

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🌈 EXAMPLE 🌈

asimut -b -i init_add adder_32 adder_patterns res_add

so this one simulates a behavioural description held in the file named 'adder_32.vbe using the pattern file `adder_patterns.pat'. the simulation results are written into 'res_add.pat' and the description is initialized with the values contained in 'init_add.sav'. 🪄

ngl the original has a slightly cursed mix of quote characters in this example — 'adder_32.vbe, `adder_patterns.pat' — and we're keeping it exactly as-is because the facts do not change, only the vibe does 💅

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💀 DIAGNOSTICS 💀

register initializations in the pattern file allow changing the value of a register into a known value. however, using this feature to initialize a register before executing the first pattern is not recommended 🙈. register values (defined by the initialization statement) may be overwritten, since the description has not got a coherent state before the first pattern. so like... don't do it, bestie, it's giving undefined behaviour energy.

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🧚 SEE ALSO 🧚

vhdl(5), pat(5), genpat(1), mbk(1) — go read them, they're the supporting cast and they ate 💖

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🔥 BUG REPORT 🔥

this tool is under development at the ASIM department of the LIP6 laboratory. we need your feedback to improve documentation and tools. 🫶 please, the devs are literally asking, send them the tea.

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okay that's the whole page, sending you off with love 💜

sign-off time: this iconic little doc comes to you courtesy of ASIM/LIP6, dated October 1, 1997 — vintage but still serving, periodt ⭐🎀