BOOM(1)

πŸ“¦ version 5.1.1-unstable-2025-02, in nixos 26.05, nixpkgs unstable

πŸ’– BOOM β€” BOOlean Minimization πŸ’–

okay bestie so this is BOOM(1), like the CAO-VLSI Reference Manual girlies know ✨ she's the boolean-minimization baddie and she's about to eat


🌸 ORIGIN 🌸

so this software belongs to the ALLIANCE CAD SYSTEM, developed by the ASIM team at the LIP6 laboratory of UniversitΓ© Pierre et Marie CURIE, in Paris, France πŸ’… Paris!! the main character city fr


πŸ¦‹ SYNOPSIS πŸ¦‹

boom [-VTOAP] [-l num] [-d num] [-i num] [-a num] [-sjbgpwtmorn]
               filename [outname]

✨ DESCRIPTION ✨

BOOM is literally the first step of the synthesis process, no cap. She optimizes a behavioural description using a Reduced Ordered Binary Decision Diagram representation of logic functions β€” it's giving iconic algorithmic queen πŸ‘‘

The file filename is your input behavioural description and it must be written in vbe(5) format (non-negotiable bestie, the vibe check fails otherwise 🫢).

The resulting behavioural optimized description gets saved under the name outname, or input_name_o if you didn't give one, also in vbe(5) format. Slay. πŸ’Ύ


🌈 ENVIRONMENT VARIABLES 🌈

  • MBK_WORK_LIB(1) β€” indicates the path to the read/write directory for the session. that's the lil home base where files get read and written, iykyk πŸŽ€

πŸŽ€ OPTIONS πŸŽ€

  • -V β€” Verbose mode on. every single step of the optimization gets displayed on the standard output. she's narrating her whole life to you πŸ’…
  • -T β€” Trace mode on. some debug information gets displayed on the standard output. detective mode era πŸ”
  • -O β€” Reverses the initial Bdd variables order. flip it, reverse it, periodt πŸ”„
  • -A β€” BOOM performs a local optimization and keeps the architecture of the initial description by saving most of the intermediate signals. This mode is well-suited for big or regular circuits such as multipliers, adders ✨

By default, BOOM performs a global optimization and removes most of the intermediate signals so that the outputs are expressed in terms of the inputs or the internal registers. That mode is well-suited for random circuits such as FSMs. two completely different vibes, pick your fighter πŸ’€

  • -P β€” Uses a parameter file input_name.boom describing optimization directives and constraints. (see below for the exact syntax) πŸ‘‡
# Example of .boom file

#
# The list of auxiliary signals that have to be kept
# during optimization.
# Generally carry signals, ram address signals etc ...
#
BEGIN_KEEP

carry[3:0]
ram_address[3:0]

END

#
# The list of auxiliary signals which assigned
# expression won't be modified.
# Generally it's ram output signals.
#
BEGIN_DONT_TOUCH
ram_out[7:0]
END
  • -l num β€” Specifies the optimization level [0-3] (default is 0, low level). start low, go high, glow up πŸ“ˆ
  • -d num β€” Specifies the delay optimization percent (default is 0% delay, 100% surface). pick your struggle bestie πŸ•°οΈ
  • -i num β€” Specifies the number of iterations for the chosen optimization algorithm (for experts only). experts only!! don't come in here guessing πŸ™ˆ
  • -a num β€” Specifies the amplitude during bdd reordering (for experts only). also experts only, respectfully πŸ’œ
  • -sjbgpwtmorn β€” Specifies which algorithm has to be used for the boolean optimization. yes that is one single flag with all those letters, and yes you read it right πŸ’€

πŸ”₯ SEE ALSO πŸ”₯

boom(5), vbe(5), asimut(1), boog(1), MBK_WORK_LIB(1).

go read those too, they're the supporting cast and they deserve love 🫢


πŸ’€ BUG REPORT πŸ’€

This tool is under development at the ASIM department of the LIP6 laboratory.

We need your feedback to improve documentation and tools. fr fr, tell them what's broken, they're literally asking πŸ™


mwah πŸ’‹ that's the page! brought to you by the ASIM/LIP6 girlies, dated August 25, 2000, and it's still serving BOOM(1) realness to this very day 🌟

πŸ“¦ where this page comes from