VBE(5)

📦 version 5.1.1, in fedora 43, fedora 44

🦋 VBE 🦋

hiii bestie!! welcome to VBE(5), aka the manual page for the VHDL subset of ASIM/LIP6/CAO-VLSI lab ✨ we're doing a full read-through, no skipping, no summarizing, every single detail stays 💅

💖 NAME 💖

  • vbe — the VHDL behavioural subset. that's it, short and iconic, she doesn't need more 🫶

🌈 ORIGIN 🌈

okay so this software belongs to the ALLIANCE CAD SYSTEM, developed by the ASIM team at the LIP6 laboratory of Université Pierre et Marie CURIE, in Paris, France 🇫🇷✨

📖 DESCRIPTION 📖

so this document describes the ALLIANCE VHDL subset for behavioural data flow descriptions. that's the whole vibe of the page, everything below is details. periodt 💜

🔥 CONCURRENT STATEMENTS 🔥

in a data flow architecture, only concurrent statements are supported — and that means except process, bestie. every sequential statement, including loops, signal assignment, etc., is to be banished. gone. not invited to the function 😤

the concurrent statements that ARE allowed:

  • simple signal assignment
  • conditional signal assignment
  • selected signal assignment
  • concurrent assert statement
  • block statement

that's the list, that's the whole guest list 💅

🚌 BUSES 🚌

when you're using concurrent statements, an ordinary signal can only be assigned once. and the value of that signal has to be explicitly defined by the signal assignment — like, for example, in a selected signal assignment the value of the target signal has to be defined for every value that the select expression can take. no gaps, no "she'll figure it out" 🙈

now, that constraint can feel like a hard restriction when you're designing distributed controlled hardware (precharged line, distributed multiplexer, etc...). and to hurdle this, VHDL pulls out a special feature: guarded-resolved signals ✨

let's break it down:

  • a resolved signal is a signal declared with a resolved subtype (see vhdl(5)). a resolved subtype is a type combined with a resolution function. a resolved signal can be assigned by multiple signal assignments, and depending on the value of each driver, the resolution function determines the effective value of the signal.
  • a guarded signal is a resolved signal with drivers that can be disconected. a guarded signal must be assigned inside a block statement through a guarded signal assignment.

a distributed multiplexer may be described as:

signal Distributed_Mux : mux_bit bus;

begin

first_driver_of_mux : block (Sel1 = '1')
begin
  Distributed_Mux <= guarded Data1;
end block;

second_driver_of_mux : block (Sel2 = '1')
begin
  Distributed_Mux <= guarded Data2;
end block;

look at her go 😭 multiple drivers, one signal, resolution function doing the heavy lifting, main character energy fr fr 👑

🧚 LATCHES and REGISTERS 🧚

sequential elements must be explicitly declared using the type reg_bit or reg_vector (and they must be of kind register). and a sequential element must be assigned inside a block statement by a guarded signal assignment. no shortcuts, bestie 🎀

rising edge triggered D flip flop:

signal Reg : reg_bit register;

begin

flip_flop : block (ck = '1' and not ck'STABLE)
begin
  Reg <= guarded Din;
end block;

level sensitive latch:

signal Reg : reg_bit register;

begin

latch : block (ck = '1')
begin
  Lat <= guarded Din;
end block;

in both cases, the guard expression must depend only on one signal if the description is to be processed by the logic synthetizer (boom + boog). one signal. that's the rule 🌸

the following operators are the only ones supported:

not, and, or, xor, nor, nand, &, =, /=

they can be applied on all types supported by the subset. other standard VHDL operators (+, -, >, <, ...) have not been implemented in the present release. so don't come for her with a plus sign, she will simply not respond 💀

⏰ TIMING ⏰

timing info can be specified in behavioural descriptions using after clauses. however, those delays are currently only used for simulation. after clauses are supported but not used for synthesis and formal proof.

after clauses in block statements (for guarded signal assignments) are not supported for sequential elements (signals of kind register), but they are supported for bus elements (signals of kind bus). why? because the VHDL default disconnection time is null, and that can generate unexpected behavior for sequential elements. so yeah. watch out 🙈

in selected signal assignment, only uniform delays are supported — meaning the same After clause in all assignments. no mixing, no chaos.

the Transport option is not supported. all delays are inertial delays. periodt.

🚨 ASSERT STATEMENT 🚨

only two severity levels are supported in concurrent assert statements:

  • warning — print a warning message if the assert condition is not satisfied.
  • error — print an error message if the assert condition is not satisfied. then, stop the simulation. she said pack it up, we're done here 😭
assert statements are ignored by the logic synthesis tool. so like, they're for the simulator's eyes only bestie.

🙈 DON'T CARE 🙈

a special feature has been introduced in order to allow "don't care" specification when the logic synthtizer is targeted.

Beware : this feature is incompatible with the IEEE VHDL standard !! like, actually incompatible. not a vibe check, a real warning 🚩

so here's the deal: an output can be assigned to the value 'D' (don't care). this is taken into account by the logic synthesis tool in the optimization process. when the value of an output is 'D', the logic synthesis tool may turn it into a '1' or a '0' — dealer's choice, she's flexible 💅

and a 'D' value is understood as a '0' by the logic simulator (asimut). noted 📝

🍓 ARRAIES 🍓

arraies other than bit_vector, reg_vector, mux_vector and wor_vector are not supported. those four, that's the whole roster 👑

✨ EXAMPLES ✨

here's the description of an adder with an accumulator register. she's beautiful, she's doing a lot, let's look 🫶

entity add_accu is
port (
  clk      : in  bit;
  command  : in  bit;
  data_in  : in  bit_vector (31 downto 0);
  data_out : out bit_vector (31 downto 0);
  cry_out  : out bit;
  vdd      : in  bit;
  vss      : in  bit
  );
end add_accu;

architecture data_flow of add_accu is

signal eff_data  : bit_vector (31 downto 0);      -- effective operande
signal adder_out : bit_vector (31 downto 0);      -- adder's result
signal adder_cry : bit_vector (32 downto 0);      -- adder's carry
signal accum_reg : reg_vector (31 downto 0) register;  -- accumulator

constant initialize : bit := '0';
constant accumulate : bit := '1';

begin

  -- select the effective operand

  with command select
  eff_data <= X"0000_0000" when initialize,
              accum_reg    when accumulate;

  -- compute the result out of the adder

  adder_out               <= eff_data xor data_in xor adder_cry;
  adder_cry (0)           <= '0';
  adder_cry (32 downto 1) <= (eff_data and adder_cry (31 downto 0)) or
                             (data_in  and adder_cry (31 downto 0)) or
                             (aff_data and data_in                ) ;

  -- write the result into the register on the rising edge of clk

  write : block (clk = '1' and not clk'STABLE)
  begin
    accum_reg <= guarded adder_out;
  end block;

  -- assign outputs

  cry_out  <= adder_cry (32);
  data_out <= accum_reg     ;

  -- check power supply

  assert (vdd = '1' and vss = '0')
  report "power sypply is missing"
  severity ERROR;

end;

not me reading this whole thing like it's a text from my bestie 😭 it's giving structured, it's giving concurrent, it's giving everything.

👀 SEE ALSO 👀

go read them, iykyk 🦋

💌 BUG REPORT 💌

this tool is under development at the ASIM department of the LIP6 laboratory.

we need your feedback to improve documentation and tools. so like, actually tell them stuff bestie, they're asking nicely 🥺🫶

okay and that's the whole page!! she came from ASIM/LIP6, dated October 1, 1997, and she's the VBE(5) manual through and through 💖 no cap, every flag, every clause, every typo, every warning — all present and accounted for. slay 💅✨🌈

📦 where this page comes from