section 9 · Kernel routines 🧠

D (continued)

• dw_hdmi_qp_rockchip_get_vop_format(9)get the bus format VOP should output✨
• dw_mci_exynos_resume_noirq(9)Exynos-specific resume code✨
• dw_mci_exynos_suspend_noirq(9)Exynos-specific suspend code✨
• dw_pcie_ep_cleanup(9)Cleanup DWC EP resources after fundamental reset✨
• dw_pcie_ep_deinit(9)Deinitialize the endpoint device✨
• dw_pcie_ep_get_func_from_ep(9)Get the struct dw_pcie_ep_func corresponding to the endpoint function✨
• dw_pcie_ep_init(9)Initialize the endpoint device✨
• dw_pcie_ep_init_registers(9)Initialize DWC EP specific registers✨
• dw_pcie_ep_linkdown(9)Notify EPF drivers about Link Down event✨
• dw_pcie_ep_linkup(9)Notify EPF drivers about Link Up event✨
• dw_pcie_ep_raise_intx_irq(9)Raise INTx IRQ to the host✨
• dw_pcie_ep_raise_msi_irq(9)Raise MSI IRQ to the host✨
• dw_pcie_ep_raise_msix_irq(9)Raise MSI-X to the host✨
• dw_pcie_ep_raise_msix_irq_doorbell(9)Raise MSI-X to the host using Doorbell method✨
• dw_pcie_ep_reset_bar(9)Reset endpoint BAR✨
• dw_pcie_wait_for_link(9)Wait for the PCIe link to be up✨
• dwarf_cfa_execute_insns(9)execute instructions to calculate a CFA✨
• dwarf_entry_len(9)return the length of an FDE or CIE✨
• dwarf_frame_alloc_reg(9)allocate memory for a DWARF register✨
• dwarf_frame_reg(9)return a DWARF register✨
• dwarf_free_frame(9)free the memory allocated for @frame✨
• dwarf_lookup_cie(9)locate the cie✨
• dwarf_lookup_fde(9)locate the FDE that covers pc✨
• dwarf_parse_section(9)parse DWARF section✨
• dwarf_read_addr(9)read dwarf data✨
• dwarf_read_encoded_value(9)return the decoded value at @addr✨
• dwarf_read_leb128(9)read signed LEB128 data✨
• dwarf_read_uleb128(9)read unsigned LEB128 data✨
• dwarf_unwind_stack(9)unwind the stack✨
• dwarf_unwinder_init(9)initialise the dwarf unwinder✨
• dwc2_assign_and_init_hc(9)Assigns transactions from a QTD to a free host channel and initializes the host channel to perform the transactions. The host channel is removed from the free list.✨
• dwc2_backup_device_registers(9)Backup controller device registers. When suspending usb bus, registers needs to be backuped if controller power is disabled once suspended.✨
• dwc2_backup_global_registers(9)Backup global controller registers. When suspending usb bus, registers needs to be backuped if controller power is disabled once suspended.✨
• dwc2_backup_host_registers(9)Backup controller host registers. When suspending usb bus, registers needs to be backuped if controller power is disabled once suspended.✨
• dwc2_calc_frame_interval(9)Calculates the correct frame Interval value for the HFIR register according to PHY type and speed✨
• dwc2_check_core_endianness(9)Returns true if core and AHB have opposite endianness.✨
• dwc2_check_core_version(9)Check core version✨
• dwc2_check_max_xfer_size(9)Checks that the max transfer size allowed in a host channel is large enough to handle the maximum data transfer in a single (micro)frame for a periodic transfer✨
• dwc2_check_periodic_bandwidth(9)Checks that there is sufficient bandwidth for the specified QH in the periodic schedule✨
• dwc2_clear_force_mode(9)Clears the force mode bits.✨
• dwc2_core_host_init(9)Initializes the DWC_otg controller registers for Host mode✨
• dwc2_core_init(9)Initializes the DWC_otg controller registers and prepares the core for device mode or host mode operation✨
• dwc2_deschedule_periodic(9)Removes an interrupt or isochronous transfer from the periodic schedule✨
• dwc2_disable_global_interrupts(9)Disables the controller's Global Interrupt in the AHB Config register✨
• dwc2_disable_host_interrupts(9)Disables the Host Mode interrupts✨
• dwc2_do_reserve(9)Make a periodic reservation✨
• dwc2_do_unreserve(9)Actually release the periodic reservation✨
• dwc2_driver_probe(9)Called when the DWC_otg core is bound to the DWC_otg driver✨
• dwc2_driver_remove(9)Called when the DWC_otg core is unregistered with the DWC_otg driver✨
• dwc2_driver_shutdown(9)Called on device shutdown✨
• dwc2_dump_channel_info(9)Prints the state of a host channel✨
• dwc2_dump_global_registers(9)Prints the core global registers✨
• dwc2_dump_host_registers(9)Prints the host registers✨
• dwc2_enable_common_interrupts(9)Initializes the commmon interrupts, used in both device and host modes✨
• dwc2_enable_global_interrupts(9)Enables the controller's Global Interrupt in the AHB Config register✨
• dwc2_enable_host_interrupts(9)Enables the Host mode interrupts✨
• dwc2_enter_partial_power_down(9)Put controller in Partial Power Down.✨
• dwc2_exit_partial_power_down(9)Exit controller from Partial Power Down.✨
• dwc2_flush_rx_fifo(9)Flushes the Rx FIFO✨
• dwc2_flush_tx_fifo(9)Flushes a Tx FIFO✨
• dwc2_force_mode(9)Force the mode of the controller.✨
• dwc2_gadget_dec_frame_num_by_one(9)Decrements the targeted frame number by one.✨
• dwc2_gadget_enter_clock_gating(9)Put controller in clock gating.✨
• dwc2_gadget_enter_hibernation(9)Put controller in Hibernation.✨
• dwc2_gadget_enter_partial_power_down(9)Put controller in partial power down.✨
• dwc2_gadget_ep_set_wedge(9)set wedge on a given endpoint✨
• dwc2_gadget_exit_hibernation(9)✨
• dwc2_gadget_get_chain_limit(9)get the maximum data payload value of the DMA descriptor chain prepared for specific endpoint✨
• dwc2_gadget_handle_ep_disabled(9)handle DXEPINT_EPDISBLD✨
• dwc2_gadget_handle_incomplete_isoc_in(9)handle incomplete ISO IN Interrupt.✨
• dwc2_gadget_handle_incomplete_isoc_out(9)handle incomplete ISO OUT Interrupt✨
• dwc2_gadget_handle_nak(9)handle NAK interrupt✨
• dwc2_gadget_handle_out_token_ep_disabled(9)handle DXEPINT_OUTTKNEPDIS✨
• dwc2_gadget_incr_frame_num(9)Increments the targeted frame number.✨
• dwc2_gadget_init(9)init function for gadget✨
• dwc2_gadget_init_lpm(9)Configure the core to support LPM in device mode✨
• dwc2_gadget_program_ref_clk(9)Program GREFCLK register in device mode✨
• dwc2_gadget_read_ep_interrupts(9)reads interrupts for given ep✨
• dwc2_gadget_start_next_request(9)Starts next request from ep queue✨
• dwc2_gadget_target_frame_elapsed(9)Checks target frame✨
• dwc2_gadget_wkup_alert_handler(9)Handler for WKUP_ALERT interrupt✨
• dwc2_get_device_properties(9)Read in device properties.✨
• dwc2_get_hwparams(9)During device initialization, read various hardware configuration registers and interpret the contents.✨
• dwc2_get_ls_map(9)Get the map used for the given qh✨
• dwc2_handle_conn_id_status_change_intr(9)Handles the Connector ID Status Change Interrupt✨
• dwc2_handle_hcd_intr(9)Called on every hardware interrupt✨
• dwc2_handle_lpm_intr(9)GINTSTS_LPMTRANRCVD Interrupt handler✨
• dwc2_handle_mode_mismatch_intr(9)Logs a mode mismatch warning message✨
• dwc2_handle_otg_intr(9)Handles the OTG Interrupts. It reads the OTG Interrupt Register (GOTGINT) to determine what interrupt has occurred.✨
• dwc2_handle_session_req_intr(9)This interrupt indicates that a device is initiating the Session Request Protocol to request the host to turn on bus power so a new session can begin✨
• dwc2_handle_usb_port_intr(9)handles OTG PRTINT interrupts. When the PRTINT interrupt fires, there are certain status bits in the Host Port that needs to get cleared.✨
• dwc2_hc_cleanup(9)Clears the transfer state for a host channel✨
• dwc2_hc_continue_transfer(9)Continues a data transfer that was started by a previous call to dwc2_hc_start_transfer()✨
• dwc2_hc_do_ping(9)Starts a PING transfer✨
• dwc2_hc_halt(9)Attempts to halt a host channel✨
• dwc2_hc_init(9)Prepares a host channel for transferring packets to/from a specific endpoint✨
• dwc2_hc_set_even_odd_frame(9)Sets the channel property that indicates in which frame a periodic transfer should occur✨
• dwc2_hc_start_transfer(9)Does the setup for a data transfer for a host channel and starts the transfer✨
• dwc2_hc_start_transfer_ddma(9)Does the setup for a data transfer for a host channel and starts the transfer in Descriptor DMA mode✨
• dwc2_hc_write_packet(9)Writes a packet into the Tx FIFO associated with the Host Channel✨
• dwc2_hcd_complete_xfer_ddma(9)Scans the descriptor list, updates URB's status and calls completion routine for the URB if it's done. Called from interrupt handlers.✨
• dwc2_hcd_connect(9)Handles connect of the HCD✨
• dwc2_hcd_disconnect(9)Handles disconnect of the HCD✨
• dwc2_hcd_dump_state(9)Dumps hsotg state✨
• dwc2_hcd_is_b_host(9)Returns 1 if core currently is acting as B host, and 0 otherwise✨
• dwc2_hcd_qh_add(9)Adds a QH to either the non periodic or periodic schedule if it is not already in the schedule. If the QH is already in the schedule, no action is taken.✨
• dwc2_hcd_qh_create(9)Allocates and initializes a QH✨
• dwc2_hcd_qh_free(9)Frees the QH✨
• dwc2_hcd_qh_free_ddma(9)Frees a QH structure's Descriptor DMA related members✨
• dwc2_hcd_qh_init_ddma(9)Initializes a QH structure's Descriptor DMA related members✨
• dwc2_hcd_qh_unlink(9)Removes a QH from either the non-periodic or periodic schedule. Memory is not freed.✨
• dwc2_hcd_qtd_add(9)Adds a QTD to the QTD-list of a QH Caller must hold driver lock.✨
• dwc2_hcd_qtd_init(9)Initializes a QTD structure✨
• dwc2_hcd_queue_transactions(9)Processes the currently active host channels and queues transactions for these channels to the DWC_otg controller. Called from the HCD interrupt handler functions.✨
• dwc2_hcd_rem_wakeup(9)Handles Remote Wakeup✨
• dwc2_hcd_select_transactions(9)Selects transactions from the HCD transfer schedule and assigns them to available host channels. Called from the HCD interrupt handler functions.✨
• dwc2_hcd_start(9)Starts the HCD when switching to Host mode✨
• dwc2_hcd_start_xfer_ddma(9)Starts a transfer in Descriptor DMA mode✨
• dwc2_hcd_stop(9)Halts the DWC_otg host mode operation✨
• dwc2_hib_restore_common(9)Common part of restore routine.✨
• dwc2_host_enter_clock_gating(9)Put controller in clock gating.✨
• dwc2_host_enter_hibernation(9)Put controller in Hibernation.✨
• dwc2_host_enter_partial_power_down(9)Put controller in partial power down.✨
• dwc2_host_exit_clock_gating(9)Exit controller from clock gating.✨
• dwc2_host_get_tt_info(9)Get the dwc2_tt associated with context✨
• dwc2_host_put_tt_info(9)Put the dwc2_tt from dwc2_host_get_tt_info()✨
• dwc2_hs_pmap_schedule(9)Schedule in the main high speed schedule✨
• dwc2_hs_pmap_unschedule(9)Undo work done by dwc2_hs_pmap_schedule()✨
• dwc2_hsotg_complete_in(9)complete IN transfer✨
• dwc2_hsotg_complete_oursetup(9)setup completion callback✨
• dwc2_hsotg_complete_request(9)complete a request given to us✨
• dwc2_hsotg_complete_setup(9)completion of a setup transfer✨
• dwc2_hsotg_core_init_disconnected(9)issue softreset to the core✨
• dwc2_hsotg_create_debug(9)create debugfs directory and files✨
• dwc2_hsotg_ctrl_epint(9)enable/disable an endpoint irq✨
• dwc2_hsotg_disable_gsint(9)disable one or more of the general interrupt✨
• dwc2_hsotg_disconnect(9)disconnect service✨
• dwc2_hsotg_dump(9)dump state of the udc✨
• dwc2_hsotg_en_gsint(9)enable one or more of the general interrupt✨
• dwc2_hsotg_enqueue_setup(9)start a request for EP0 packets✨
• dwc2_hsotg_ep0_mps(9)turn max packet size into register setting✨
• dwc2_hsotg_ep0_zlp(9)send/receive zero-length packet on control endpoint✨
• dwc2_hsotg_ep_alloc_request(9)allocate USB rerequest structure✨
• dwc2_hsotg_ep_dequeue(9)dequeue given endpoint✨
• dwc2_hsotg_ep_disable(9)disable given endpoint✨
• dwc2_hsotg_ep_enable(9)enable the given endpoint✨
• dwc2_hsotg_ep_sethalt(9)set halt on a given endpoint✨
• dwc2_hsotg_ep_sethalt_lock(9)set halt on a given endpoint with lock held✨
• dwc2_hsotg_epint(9)handle an in/out endpoint interrupt✨
• dwc2_hsotg_gadget_getframe(9)read the frame number✨
• dwc2_hsotg_handle_outdone(9)handle receiving OutDone/SetupDone from RXFIFO✨
• dwc2_hsotg_handle_rx(9)RX FIFO has data✨
• dwc2_hsotg_hw_cfg(9)read HW configuration registers✨
• dwc2_hsotg_init(9)initialize the usb core✨
• dwc2_hsotg_init_fifo(9)initialise non-periodic FIFOs✨
• dwc2_hsotg_initep(9)initialise a single endpoint✨
• dwc2_hsotg_irq(9)handle device interrupt✨
• dwc2_hsotg_irq_enumdone(9)Handle EnumDone interrupt (enumeration done)✨
• dwc2_hsotg_irq_fifoempty(9)TX FIFO empty interrupt handler✨
• dwc2_hsotg_map_dma(9)map the DMA memory being used for the request✨
• dwc2_hsotg_process_control(9)process a control request✨
• dwc2_hsotg_process_req_feature(9)process request {SET,CLEAR}_FEATURE✨
• dwc2_hsotg_process_req_status(9)process request GET_STATUS✨
• dwc2_hsotg_pullup(9)connect/disconnect the USB PHY✨
• dwc2_hsotg_read_frameno(9)read current frame number✨
• dwc2_hsotg_remove(9)remove function for hsotg driver✨
• dwc2_hsotg_rx_data(9)receive data from the FIFO for an endpoint✨
• dwc2_hsotg_send_reply(9)send reply to control request✨
• dwc2_hsotg_set_ep_maxpacket(9)set endpoint's max-packet field✨
• dwc2_hsotg_set_selfpowered(9)set if device is self/bus powered✨
• dwc2_hsotg_set_test_mode(9)Enable usb Test Modes✨
• dwc2_hsotg_stall_ep0(9)stall ep0✨
• dwc2_hsotg_start_req(9)start a USB request from an endpoint's queue✨
• dwc2_hsotg_trytx(9)check to see if anything needs transmitting✨
• dwc2_hsotg_tx_fifo_average_depth(9)returns average depth of device mode TX FIFOs✨
• dwc2_hsotg_tx_fifo_count(9)return count of TX FIFOs in device mode✨
• dwc2_hsotg_tx_fifo_total_depth(9)return total FIFO depth available for device mode TX FIFOs✨
• dwc2_hsotg_txfifo_flush(9)flush Tx FIFO✨
• dwc2_hsotg_udc_start(9)prepare the udc for work✨
• dwc2_hsotg_udc_stop(9)stop the udc✨
• dwc2_hsotg_unmap_dma(9)unmap the DMA memory being used for the request✨
• dwc2_hsotg_vbus_draw(9)report bMaxPower field✨
• dwc2_hsotg_wait_bit_clear(9)Waits for bit to be clear.✨
• dwc2_hsotg_wait_bit_set(9)Waits for bit to be set.✨
• dwc2_hsotg_write_fifo(9)write packet Data to the TxFIFO✨
• dwc2_iddig_filter_enabled(9)Returns true if the IDDIG debounce filter is enabled.✨
• dwc2_lowlevel_hw_disable(9)disable platform lowlevel hw resources✨
• dwc2_lowlevel_hw_enable(9)enable platform lowlevel hw resources✨
• dwc2_ls_pmap_schedule(9)Schedule a low speed QH✨
• dwc2_ls_pmap_unschedule(9)Undo work done by dwc2_ls_pmap_schedule()✨
• dwc2_next_for_periodic_split(9)Set next_active_frame midway thru a split.✨
• dwc2_next_periodic_start(9)Set next_active_frame for next transfer start✨
• dwc2_pci_remove(9)Provides the cleanup entry points for the DWC_otg PCI driver✨
• dwc2_periodic_channel_available(9)Checks that a channel is available for a periodic transfer✨
• dwc2_pick_first_frame(9)Choose 1st frame for qh that's already scheduled✨
• dwc2_port_resume(9)Exit controller from suspend mode for host.✨
• dwc2_port_suspend(9)Put controller in suspend mode for host.✨
• dwc2_qh_init(9)Initializes a QH structure✨
• dwc2_qh_print(9)Helper function for dwc2_qh_schedule_print()✨
• dwc2_qh_schedule_print(9)Print the periodic schedule✨