dwc2_hcd_complete_xfer_ddma(9)

📦 version 7.3.1, in nixpkgs unstable

💅 dwc2_hcd_complete_xfer_ddma(9) 💅

okay so bestie, welcome to the Kernel API Manual — today’s main character is dwc2_hcd_complete_xfer_ddma(9), and she is lowkey doing important work. 🫶

🌸 NAME 🌸

okay so dwc2_hcd_complete_xfer_ddma scans the descriptor list, updates URB's status, and calls the completion routine for the URB if it's done. She’s called from interrupt handlers, bestie — interrupt-handler energy fr fr. 😭💖

✨ SYNOPSIS ✨

void dwc2_hcd_complete_xfer_ddma (struct dwc2_hsotg *hsotg , struct dwc2_host_chan *chan , int chnum , enum dwc2_halt_status halt_status );

🎀 ARGUMENTS 🎀

  • hsotg — the HCD state structure for the DWC OTG controller. that’s the whole state-structure vibe 👑
  • chan — the Host channel the transfer is completed on. yep, that channel 💅
  • chnum — index of Host channel registers. literally the register index, no cap ✨
  • halt_status — reason the channel is being halted, or just XferComplete for isochronous transfers. keeping it real 🦋

🦋 DESCRIPTION 🦋

Bestie, she releases the channel to be used by other transfers — sharing is caring, periodt. 💖

In case of Isochronous endpoint, the channel is not halted until the end of the session, i.e. until the QTD list is empty. 🌈

If a periodic channel is released, the FrameList is updated accordingly. 📋✨

She also calls transaction selection routines to activate pending transfers — activating pending transfers is her little side quest, and she ate. 🔥👑

💜 SEE ALSO 💜

Kernel file ./drivers/usb/dwc2/hcd_ddma.c — yes bestie, that’s the spot 🧚

Signing off from source/version ./drivers/usb/dwc2, dated October 2026 — mwah 💋, and yes, this page is still dwc2_hcd_complete_xfer_ddma(9) 💖🎀

📦 where this page comes from