dwc2_hc_start_transfer(9)

🎀 dwc2_hc_start_transfer(9) 🎀

okay bestie, welcome to the Kernel API Manual entry for dwc2_hc_start_transfer — the host-channel transfer setup function that is genuinely doing the most so your data transfer can simply exist. It’s giving “small function, big USB energy” ✨.

🌸 NAME 🌸

dwc2_hc_start_transfer — does the setup for a data transfer for a host channel and starts the transfer. Like, it preps the whole situation and then hits go. No cap. 💅

✨ SYNOPSIS ✨

void dwc2_hc_start_transfer (struct dwc2_hsotg *hsotg , struct
       dwc2_host_chan *chan );

💖 ARGUMENTS 💖

• hsotg — the programming view of the DWC_otg controller. That’s the controller’s main-character data, iykyk. 👑
• chan — the information needed to initialize the host channel. Heads up: the xfer_len value may be reduced to accommodate the max widths of the XferSize and PktCnt fields in the HCTSIZn register, and the multi_count value may be changed to reflect the final xfer_len value. The way that’s a whole little fine-print moment 💀.

🦋 DESCRIPTION 🦋

This function may be called in either Slave mode or DMA mode. In Slave mode, the caller must ensure that there is sufficient space in the request queue and Tx Data FIFO. Like, actually ensure it — no vibes-only checking, bestie 😌.

For an OUT transfer in Slave mode, it loads a data packet into the appropriate FIFO. If necessary, additional data packets are loaded in the Host ISR. Slay, but make it FIFO 🎀.

For an IN transfer in Slave mode, a data packet is requested. The data packets are unloaded from the Rx FIFO in the Host ISR. If necessary, additional data packets are requested in the Host ISR. The Host ISR is lowkey doing the most here 💅.

For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ register along with a packet count of 1 and the channel is enabled. This causes a single PING transaction to occur. Other fields in HCTSIZ are simply set to 0 since no data transfer occurs in this case. Iconic little ping-only moment ✨.

For a PING transfer in DMA mode, the HCTSIZ register is initialized with all the information required to perform the subsequent data transfer. In addition, the Do Ping bit is set in the HCTSIZ register. In this case, the controller performs the entire PING protocol, then starts the data transfer. It’s giving “ping first, transfer later,” and honestly? Obsessed 🔥.

👑 SEE ALSO 👑

Kernel file ./drivers/usb/dwc2/hcd.c — go read these too, bestie:

• dwc2_enable_common_interrupts(9)
• dwc2_enable_host_interrupts(9)
• dwc2_disable_host_interrupts(9)
• dwc2_calc_frame_interval(9)
• dwc2_read_packet(9)
• dwc2_dump_channel_info(9)
• dwc2_hc_init(9)
• dwc2_hc_halt(9)
• dwc2_hc_cleanup(9)
• dwc2_hc_set_even_odd_frame(9)
• dwc2_hc_write_packet(9)
• dwc2_hc_do_ping(9)
• dwc2_hc_start_transfer_ddma(9)
• dwc2_hc_continue_transfer(9)
• dwc2_hcd_start(9)
• dwc2_hcd_connect(9)
• dwc2_hcd_disconnect(9)
• dwc2_hcd_rem_wakeup(9)
• dwc2_hcd_stop(9)
• dwc2_core_init(9)
• dwc2_core_host_init(9)
• dwc2_assign_and_init_hc(9)
• dwc2_hcd_select_transactions(9)
• dwc2_queue_transaction(9)
• dwc2_hcd_queue_transactions(9)
• dwc2_port_suspend(9)
• dwc2_port_resume(9)
• dwc2_host_get_tt_info(9)
• dwc2_host_put_tt_info(9)
• dwc2_backup_host_registers(9)
• dwc2_restore_host_registers(9)
• dwc2_host_enter_hibernation(9)
• dwc2_host_enter_partial_power_down(9)
• dwc2_host_enter_clock_gating(9)
• dwc2_host_exit_clock_gating(9)

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xoxo, your Kernel API Manual bestie 🫶 — this cutie is the dwc2_hc_start_transfer(9) page from source/version ./drivers/usb/dwc2, dated October 2026. Bye bestie, go start that transfer responsibly 💖🌈