section 9 · Kernel routines 🧠

A (continued)

• amdgpu_gfx_set_run_cleaner_shader(9)Execute the AMDGPU GFX Cleaner Shader✨
• amdgpu_gmc_agp_addr(9)return the address in the AGP address space✨
• amdgpu_gmc_agp_location(9)try to find AGP location✨
• amdgpu_gmc_fault_key(9)get hask key from vm fault address and pasid✨
• amdgpu_gmc_filter_faults(9)filter VM faults✨
• amdgpu_gmc_filter_faults_remove(9)remove address from VM faults filter✨
• amdgpu_gmc_gart_location(9)try to find GART location✨
• amdgpu_gmc_get_pde_for_bo(9)get the PDE for a BO✨
• amdgpu_gmc_init_pdb0(9)initialize PDB0✨
• amdgpu_gmc_noretry_set(9)- set per asic noretry defaults✨
• amdgpu_gmc_pdb0_alloc(9)allocate vram for pdb0✨
• amdgpu_gmc_set_agp_default(9)Set the default AGP aperture value.✨
• amdgpu_gmc_set_pte_pde(9)update the page tables using CPU✨
• amdgpu_gmc_sign_extend(9)sign extend the given gmc address✨
• amdgpu_gmc_tmz_set(9)- check and set if a device supports TMZ✨
• amdgpu_gmc_vram_full_visible(9)Check if full VRAM is visible through the BAR✨
• amdgpu_gmc_vram_location(9)try to find VRAM location✨
• amdgpu_gmc_vram_mc2pa(9)calculate vram buffer's physical address from MC address✨
• amdgpu_gmc_vram_pa(9)calculate vram buffer object's physical address from GPU's view✨
• amdgpu_gtt_mgr_alloc_entries(9)alloc GART entries without GTT bo✨
• amdgpu_gtt_mgr_compatible(9)test for compatibility✨
• amdgpu_gtt_mgr_debug(9)dump VRAM table✨
• amdgpu_gtt_mgr_del(9)free ranges✨
• amdgpu_gtt_mgr_fini(9)free and destroy GTT manager✨
• amdgpu_gtt_mgr_free_entries(9)free GART entries not accocaited with GTT bo✨
• amdgpu_gtt_mgr_has_gart_addr(9)Check if mem has address space✨
• amdgpu_gtt_mgr_init(9)init GTT manager and DRM MM✨
• amdgpu_gtt_mgr_intersects(9)test for intersection✨
• amdgpu_gtt_mgr_mark_bo_teardown(9)exclude a BO from GART recovery✨
• amdgpu_gtt_mgr_new(9)allocate a new node✨
• amdgpu_gtt_mgr_recover(9)re-init gart✨
• amdgpu_gtt_node_to_byte_offset(9)Returns a byte offset of a gtt node✨
• amdgpu_hmm_invalidate_gfx(9)callback to notify about mm change✨
• amdgpu_hmm_invalidate_hsa(9)callback to notify about mm change✨
• amdgpu_hmm_range_alloc(9)allocate and initialize an AMDGPU HMM range✨
• amdgpu_hmm_range_free(9)release an AMDGPU HMM range✨
• amdgpu_hmm_range_valid(9)check if an HMM range is still valid✨
• amdgpu_hmm_register(9)register a BO for notifier updates✨
• amdgpu_hmm_unregister(9)unregister a BO for notifier updates✨
• amdgpu_ib_free(9)free an IB (Indirect Buffer)✨
• amdgpu_ib_get(9)request an IB (Indirect Buffer)✨
• amdgpu_ib_pool_fini(9)Free the IB (Indirect Buffer) pool✨
• amdgpu_ib_pool_gfp_flags(9)Returns the gfp flags to use for each pool✨
• amdgpu_ib_pool_init(9)Init the IB (Indirect Buffer) pool✨
• amdgpu_ib_ring_tests(9)test IBs on the rings✨
• amdgpu_ib_schedule(9)schedule an IB (Indirect Buffer) on the ring✨
• amdgpu_ih_decode_iv_helper(9)decode an interrupt vector✨
• amdgpu_ih_process(9)interrupt handler✨
• amdgpu_ih_ring_fini(9)tear down the IH state✨
• amdgpu_ih_ring_init(9)initialize the IH state✨
• amdgpu_ih_ring_write(9)write IV to the ring buffer✨
• amdgpu_ih_wait_on_checkpoint_process_ts(9)wait to process IVs up to checkpoint✨
• amdgpu_info_ioctl(9)answer a device specific request.✨
• amdgpu_ip_from_ring(9)Find IP block type corresponding to ring type.✨
• amdgpu_irq_add_domain(9)create a linear IRQ domain✨
• amdgpu_irq_add_id(9)register IRQ source✨
• amdgpu_irq_create_mapping(9)create mapping between domain Linux IRQs✨
• amdgpu_irq_delegate(9)delegate IV to soft IH ring✨
• amdgpu_irq_disable_all(9)disable *all* interrupts✨
• amdgpu_irq_dispatch(9)dispatch IRQ to IP blocks✨
• amdgpu_irq_enabled(9)check whether interrupt is enabled or not✨
• amdgpu_irq_fini_sw(9)shut down interrupt handling✨
• amdgpu_irq_get(9)enable interrupt✨
• amdgpu_irq_gpu_reset_resume_helper(9)update interrupt states on all sources✨
• amdgpu_irq_handle_ih1(9)kick of processing for IH1✨
• amdgpu_irq_handle_ih2(9)kick of processing for IH2✨
• amdgpu_irq_handle_ih_soft(9)kick of processing for ih_soft✨
• amdgpu_irq_handler(9)IRQ handler✨
• amdgpu_irq_init(9)initialize interrupt handling✨
• amdgpu_irq_put(9)disable interrupt✨
• amdgpu_irq_remove_domain(9)remove the IRQ domain✨
• amdgpu_irq_update(9)update hardware interrupt state✨
• amdgpu_irqdomain_map(9)create mapping between virtual and hardware IRQ numbers✨
• amdgpu_jpeg_dec_parse_cs(9)command submission parser✨
• amdgpu_lockdep_init(9)Train lockdep on correct lock ordering✨
• amdgpu_lockdep_set_class(9)Associate lock class keys with real locks✨
• amdgpu_max_hdmi_pixel_clock(9)Return max supported HDMI (TMDS) pixel clock✨
• amdgpu_mem_type_to_domain(9)return domain corresponding to mem_type✨
• amdgpu_mes_alloc_proc_ctx_index(9)allocate a process context slot✨
• amdgpu_mes_rs64mem_init(9)initialize RS64 local memory context arrays✨
• amdgpu_mes_rs64mem_setup_bitmaps(9)allocate bitmaps after querying MES✨
• amdgpu_mm_rdoorbell(9)read a doorbell dword✨
• amdgpu_mm_rdoorbell64(9)read a doorbell Qword✨
• amdgpu_mm_rreg8(9)read a memory mapped IO register✨
• amdgpu_mm_wdoorbell(9)write a doorbell dword✨
• amdgpu_mm_wdoorbell64(9)write a doorbell Qword✨
• amdgpu_mm_wreg8(9)read a memory mapped IO register✨
• amdgpu_mm_wreg_mmio_rlc(9)write register either with direct/indirect mmio or with RLC path if in range✨
• amdgpu_msi_ok(9)check whether MSI functionality is enabled✨
• amdgpu_multi_ring_reset_helper_begin(9)Prepare multiple rings for a reset.✨
• amdgpu_multi_ring_reset_helper_end(9)Prepare multiple rings for a reset.✨
• amdgpu_object(9)✨
• amdgpu_pasid_alloc(9)Allocate a PASID✨
• amdgpu_pasid_clear_owner(9)Clear the owner associated with a PASID✨
• amdgpu_pasid_free(9)Free a PASID✨
• amdgpu_pasid_free_delayed(9)free pasid when fences signal✨
• amdgpu_pasid_get_fpriv_locked(9)get the DRM owner of a PASID✨
• amdgpu_pasid_lock(9)acquire the global PASID xarray lock✨
• amdgpu_pasid_mgr_cleanup(9)cleanup PASID manager✨
• amdgpu_pasid_unlock(9)release the global PASID xarray lock✨
• amdgpu_pci_error_detected(9)Called when a PCI error is detected.✨
• amdgpu_pci_mmio_enabled(9)Enable MMIO and dump debug registers✨
• amdgpu_pci_resume(9)resume normal ops after PCI reset✨
• amdgpu_pci_slot_reset(9)Called when PCI slot has been reset.✨
• amdgpu_pll_compute(9)compute PLL paramaters✨
• amdgpu_pll_get_fb_ref_div(9)feedback and ref divider calculation✨
• amdgpu_pll_get_shared_dp_ppll(9)return the PPLL used by another crtc for DP✨
• amdgpu_pll_get_shared_nondp_ppll(9)return the PPLL used by another non- DP crtc✨
• amdgpu_pll_get_use_mask(9)look up a mask of which pplls are in use✨
• amdgpu_pll_reduce_ratio(9)fractional number reduction✨
• amdgpu_pm_dev_state_check(9)Check if device can be accessed.✨
• amdgpu_pm_get_access(9)Check if device can be accessed, resume if needed.✨
• amdgpu_pm_get_access_if_active(9)Check if device is active for access.✨
• amdgpu_pm_put_access(9)Put to auto suspend mode after a device access.✨
• amdgpu_pp_power(9)✨
• amdgpu_preempt_mgr_del(9)free ranges✨
• amdgpu_preempt_mgr_fini(9)free and destroy GTT manager✨
• amdgpu_preempt_mgr_init(9)init PREEMPT manager and DRM MM✨
• amdgpu_preempt_mgr_new(9)allocate a new node✨
• amdgpu_preempt_mgr_sysfs_fini(9)remove PREEMPT manager sysfs attributes✨
• amdgpu_proc_options_ioctl(9)set per-fd user options✨
• amdgpu_ras_eeprom_append(9)- append records to the EEPROM RAS table✨
• amdgpu_ras_eeprom_read(9)- read EEPROM✨
• amdgpu_ras_eeprom_reset_table(9)- Reset the RAS EEPROM table✨
• amdgpu_ras_query_error_count(9)- Get error counts of all IPs or specific IP✨
• amdgpu_ras_query_error_count_helper(9)- Get error counter for specific IP✨
• amdgpu_register_atpx_handler(9)register with vga_switcheroo✨
• amdgpu_res_cleared(9)check if blocks are cleared✨
• amdgpu_res_cpu_visible(9)Check that resource can be accessed by CPU✨
• amdgpu_res_first(9)initialize a amdgpu_res_cursor✨
• amdgpu_res_next(9)advance the cursor✨
• amdgpu_ring_alloc(9)allocate space on the ring buffer✨
• amdgpu_ring_commit(9)tell the GPU to execute the new commands on the ring buffer✨
• amdgpu_ring_emit_reg_write_reg_wait_helper(9)ring helper✨
• amdgpu_ring_fini(9)tear down the driver ring struct.✨
• amdgpu_ring_generic_pad_ib(9)pad IB with NOP packets✨
• amdgpu_ring_init(9)init driver ring struct.✨
• amdgpu_ring_insert_nop(9)insert NOP packets✨
• amdgpu_ring_mask_from_ip(9)Find mask of ring types corresponding to an IP block type.✨
• amdgpu_ring_max_ibs(9)Return max IBs that fit in a single submission.✨
• amdgpu_ring_mux_get_rptr(9)get the readptr of the software ring✨
• amdgpu_ring_patch_cond_exec(9)patch dw count of conditional execute✨
• amdgpu_ring_set_fence_errors_and_reemit(9)Set dma_fence errors and reemit✨
• amdgpu_ring_soft_recovery(9)try to soft recover a ring lockup✨
• amdgpu_ring_test_helper(9)tests ring and set sched readiness status✨
• amdgpu_ring_undo(9)reset the wptr✨
• amdgpu_sdma_is_shared_inv_eng(9)Check if a ring is an SDMA ring that shares a VM invalidation engine✨
• amdgpu_sdma_reset_engine(9)Reset a specific SDMA engine✨
• amdgpu_seq64(9)✨
• amdgpu_seq64_alloc(9)Allocate a 64 bit memory✨
• amdgpu_seq64_fini(9)Cleanup seq64 driver✨
• amdgpu_seq64_free(9)Free the given 64 bit memory✨
• amdgpu_seq64_get_va_base(9)Get the seq64 va base address✨
• amdgpu_seq64_init(9)Initialize seq64 driver✨
• amdgpu_seq64_map(9)Map the seq64 memory to VM✨
• amdgpu_seq64_unmap(9)Unmap the seq64 memory✨
• amdgpu_switcheroo_can_switch(9)see if switcheroo state can change✨
• amdgpu_switcheroo_set_state(9)set switcheroo state✨
• amdgpu_sync_add_later(9)add the fence to the hash✨
• amdgpu_sync_clone(9)clone a sync object✨
• amdgpu_sync_create(9)zero init sync object✨
• amdgpu_sync_fence(9)remember to sync to this fence✨
• amdgpu_sync_fini(9)fini sync object subsystem✨
• amdgpu_sync_free(9)free the sync object✨
• amdgpu_sync_get_fence(9)get the next fence from the sync object✨
• amdgpu_sync_get_owner(9)extract the owner of a fence✨
• amdgpu_sync_init(9)init sync object subsystem✨
• amdgpu_sync_keep_later(9)Keep the later fence✨
• amdgpu_sync_kfd(9)sync to KFD fences✨
• amdgpu_sync_move(9)move all fences from src to dst✨
• amdgpu_sync_peek_fence(9)get the next fence not signaled yet✨
• amdgpu_sync_push_to_job(9)push fences into job✨
• amdgpu_sync_resv(9)sync to a reservation object✨
• amdgpu_sync_same_dev(9)test if fence belong to us✨
• amdgpu_ttm_access_memory(9)Read or Write memory that backs a buffer object.✨
• amdgpu_ttm_alloc_mmio_remap_bo(9)Allocate the singleton MMIO_REMAP BO✨
• amdgpu_ttm_clear_buffer(9)fill a buffer with 0✨
• amdgpu_ttm_copy_mem_to_mem(9)Helper function for copy✨
• amdgpu_ttm_disable_buffer_funcs(9)disable use of buffer functions✨
• amdgpu_ttm_domain_start(9)Returns GPU start address✨
• amdgpu_ttm_enable_buffer_funcs(9)enable use of buffer functions✨
• amdgpu_ttm_evict_resources(9)evict memory buffers✨
• amdgpu_ttm_free_mmio_remap_bo(9)Free the singleton MMIO_REMAP BO✨
• amdgpu_ttm_map_buffer(9)Map memory into the GART windows✨
• amdgpu_ttm_mmio_remap_alloc_sgt(9)build an sg_table for MMIO_REMAP I/O aperture✨
• amdgpu_ttm_training_reserve_vram_fini(9)free memory training reserved vram✨
• amdgpu_ttm_tt_create(9)Create a ttm_tt object for a given BO✨
• amdgpu_ttm_tt_get_userptr(9)Return the userptr GTT ttm_tt for the current task✨
• amdgpu_ttm_tt_pde_flags(9)Compute PDE flags for ttm_tt object✨
• amdgpu_ttm_tt_pte_flags(9)Compute PTE flags for ttm_tt object✨
• amdgpu_ttm_tt_set_userptr(9)Initialize userptr GTT ttm_tt for the current task✨
• amdgpu_unregister_atpx_handler(9)unregister with vga_switcheroo✨
• amdgpu_userq_ensure_ev_fence(9)ensure a valid, unsignaled eviction fence exists✨
• amdgpu_userq_fence_read_wptr(9)Read the userq wptr value✨
• amdgpu_uvd_cs_msg(9)handle UVD message✨
• amdgpu_uvd_cs_msg_decode(9)handle UVD decode message✨
• amdgpu_uvd_cs_packets(9)parse UVD packets✨
• amdgpu_uvd_cs_pass1(9)first parsing round✨
• amdgpu_uvd_cs_pass2(9)second parsing round✨
• amdgpu_uvd_cs_reg(9)parse register writes✨