amdgpu_ttm_...ap_alloc_sgt(9)
πΈ amdgpu_ttm_...ap_alloc_sgt(9) β from the Kernel API Manual π
okay so bestie, welcome to the manual page for amdgpu_ttm_...ap_alloc_sgt(9) β yes the title is truncated like that, that's just how it is, no cap. Anyway, put your hair up and let's get into it π
β¨ NAME β¨
amdgpu_ttm_mmio_remap_alloc_sgt β builds an sg_table for the MMIO_REMAP I/O aperture π¦
So basically: you've got this weird little I/O window, and this function makes a scatter-gather table for it. Iconic behavior, honestly.
β¨ SYNOPSIS β¨
int amdgpu_ttm_mmio_remap_alloc_sgt (struct amdgpu_device *adev , struct
ttm_resource *res , struct device *dev , enum dma_data_direction dir ,
struct sg_table **sgt );
β¨ ARGUMENTS β¨
adevβ the amdgpu device that provides the remap BAR base, akaadev->rmmio_remap.bus_addr. She's the source of truth for where this window lives πresβ the TTM resource of the BO you're exporting. It's expected to live inAMDGPU_PL_MMIO_REMAP, like, that's its whole address. Respect it.devβ the importing device you're mapping for (typicallyattach->devin dma-buf paths). Say hi to it for me π«Άdirβ the DMA data direction for the importer, passed straight todma_map_resource. Just hand it over, don't overthink it.sgtβ the output! On success it's set to a newly allocatedsg_tabledescribing the I/O span β¨
β¨ DESCRIPTION β¨
Okay so the lore: the HDP flush page (AMDGPU_PL_MMIO_REMAP) is a fixed hardware I/O window inside a PCI BAR β and there are literally no struct pages backing it. None. Zero. It's giving ghost town π»
But importers still need a DMA address list, right? So instead of pages, we synthesize a minimal sg_table and populate it from dma_map_resource. That's the whole trick. And using the common amdgpu_res_cursor walker keeps the offset/size math consistent with the other TTM/manager users β consistency is the look, periodt π
resis assumed to be a small, contiguous I/O region (typically a single 4 KiB page) inAMDGPU_PL_MMIO_REMAP. Callers should validate placement before calling β like, do your homework first, bestie π- The sg entry is created with
sg_set_page(sg, NULL, β¦)to reflect I/O space. Yes,NULLon purpose. Not a bug. Slay. - The mapping uses
DMA_ATTR_SKIP_CPU_SYNCbecause this is MMIO, not cacheable RAM β so that CPU sync would be pointless and we skip it, as one does. - Peer reachability / p2pdma policy checks must be done by the caller. Not us. That's your main character moment, not ours π₯
β¨ RETURN β¨
0on success, with*sgtset to a valid table that must be freed viaamdgpu_ttm_mmio_remap_free_sgt. Don't forget the cleanup, it's the responsible thing to do π-ENOMEMif allocation of thesg_tablefails π-EIOifdma_map_resourcefails π
β¨ SEE ALSO β¨
The kernel file herself: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c β go read the source, iykyk π
And the whole friend group:
amdgpu_evict_flags(9)amdgpu_ttm_map_buffer(9)amdgpu_ttm_copy_mem_to_mem(9)amdgpu_res_cpu_visible(9)amdgpu_ttm_domain_start(9)amdgpu_ttm_tt_create(9)amdgpu_ttm_tt_get_userptr(9)amdgpu_ttm_tt_set_userptr(9)amdgpu_ttm_tt_pde_flags(9)amdgpu_ttm_tt_pte_flags(9)amdgpu_ttm_access_memory(9)amdgpu_ttm_training_reserve_vram_fini(9)amdgpu_ttm_alloc_mmio_remap_bo(9)amdgpu_ttm_free_mmio_remap_bo(9)amdgpu_ttm_enable_buffer_funcs(9)amdgpu_ttm_disable_buffer_funcs(9)amdgpu_ttm_clear_buffer(9)amdgpu_ttm_evict_resources(9)
and that's the page!! π this one's out of ./drivers/gpu/drm/amd/amdgpu and dated October 2026 β so like, future vibes, butterfly effect, whatever ππ bye bestie, go free that sg_table π§
π¦ where this page comes from
- nixpkgs unstable: linux-manual 7.3.1
- π girlified by deepseek-ai/DeepSeek-V4.1-Flash-1017 on : a language model's rewrite of the original, under its terms