amdgpu_ttm_...ap_alloc_sgt(9)

πŸ“¦ version 7.3.1, in nixpkgs unstable

🌸 amdgpu_ttm_...ap_alloc_sgt(9) β€” from the Kernel API Manual πŸ’…

okay so bestie, welcome to the manual page for amdgpu_ttm_...ap_alloc_sgt(9) β€” yes the title is truncated like that, that's just how it is, no cap. Anyway, put your hair up and let's get into it πŸŽ€


✨ NAME ✨

amdgpu_ttm_mmio_remap_alloc_sgt β€” builds an sg_table for the MMIO_REMAP I/O aperture πŸ¦‹

So basically: you've got this weird little I/O window, and this function makes a scatter-gather table for it. Iconic behavior, honestly.


✨ SYNOPSIS ✨

int amdgpu_ttm_mmio_remap_alloc_sgt (struct amdgpu_device *adev , struct
ttm_resource *res , struct device *dev , enum dma_data_direction dir ,
struct sg_table **sgt );

✨ ARGUMENTS ✨

  • adev β€” the amdgpu device that provides the remap BAR base, aka adev->rmmio_remap.bus_addr. She's the source of truth for where this window lives πŸ’–
  • res β€” the TTM resource of the BO you're exporting. It's expected to live in AMDGPU_PL_MMIO_REMAP, like, that's its whole address. Respect it.
  • dev β€” the importing device you're mapping for (typically attach->dev in dma-buf paths). Say hi to it for me 🫢
  • dir β€” the DMA data direction for the importer, passed straight to dma_map_resource. Just hand it over, don't overthink it.
  • sgt β€” the output! On success it's set to a newly allocated sg_table describing the I/O span ✨

✨ DESCRIPTION ✨

Okay so the lore: the HDP flush page (AMDGPU_PL_MMIO_REMAP) is a fixed hardware I/O window inside a PCI BAR β€” and there are literally no struct pages backing it. None. Zero. It's giving ghost town πŸ‘»

But importers still need a DMA address list, right? So instead of pages, we synthesize a minimal sg_table and populate it from dma_map_resource. That's the whole trick. And using the common amdgpu_res_cursor walker keeps the offset/size math consistent with the other TTM/manager users β€” consistency is the look, periodt πŸ’…

  • res is assumed to be a small, contiguous I/O region (typically a single 4 KiB page) in AMDGPU_PL_MMIO_REMAP. Callers should validate placement before calling β€” like, do your homework first, bestie πŸ™ˆ
  • The sg entry is created with sg_set_page(sg, NULL, …) to reflect I/O space. Yes, NULL on purpose. Not a bug. Slay.
  • The mapping uses DMA_ATTR_SKIP_CPU_SYNC because this is MMIO, not cacheable RAM β€” so that CPU sync would be pointless and we skip it, as one does.
  • Peer reachability / p2pdma policy checks must be done by the caller. Not us. That's your main character moment, not ours πŸ”₯

✨ RETURN ✨

  • 0 on success, with *sgt set to a valid table that must be freed via amdgpu_ttm_mmio_remap_free_sgt. Don't forget the cleanup, it's the responsible thing to do πŸ’œ
  • -ENOMEM if allocation of the sg_table fails 😭
  • -EIO if dma_map_resource fails πŸ’€

✨ SEE ALSO ✨

The kernel file herself: ./drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c β€” go read the source, iykyk πŸ“–

And the whole friend group:


and that's the page!! πŸŽ€ this one's out of ./drivers/gpu/drm/amd/amdgpu and dated October 2026 β€” so like, future vibes, butterfly effect, whatever πŸŒˆπŸ’– bye bestie, go free that sg_table 🧚

πŸ“¦ where this page comes from