amdgpu_ib_schedule(9)

πŸ“¦ version 7.3.1, in nixpkgs unstable

πŸ’… amdgpu_ib_schedule(9) β€” the Kernel API Manual, but make it cute

okay so bestie, welcome to the Kernel API Manual entry for our girl amdgpu_ib_schedule, coming at you from the amdgpu kernel docs. she's giving driver-dev main character energy and we're gonna get into all of it πŸŽ€


✨ NAME ✨

amdgpu_ib_schedule β€” schedule an IB (that's an Indirect Buffer, iykyk) on the ring. literally her whole job πŸ’…


πŸ¦‹ SYNOPSIS πŸ¦‹

int amdgpu_ib_schedule (struct amdgpu_ring *ring , unsigned int num_ibs
, struct amdgpu_ib *ibs , struct amdgpu_job *job , struct dma_fence **f
);

πŸŽ€ ARGUMENTS πŸŽ€

  • ring β€” the ring index this IB is associated with. it's giving "where does this belong" energy 🌸
  • num_ibs β€” how many IBs we're scheduling. the count, the number, the vibe check βœ…
  • ibs β€” the actual IB objects to schedule. these are the ones doing the work fr fr 🫢
  • job β€” the job to schedule. yes bestie, a whole job πŸ—‚οΈ
  • f β€” the fence created during this submission. keeping things orderly, no cap πŸ”₯

πŸ’– DESCRIPTION πŸ’–

So the whole point: schedule an IB on the associated ring, and this applies to all asics (yes, all of them, we love an inclusive queen πŸ‘‘). She returns 0 on success, and an error on failure. periodt.

Now buckle up because here's the lore, and honestly it's iconic:

On SI, there are two parallel engines fed from the primary ring β€” the CE (Constant Engine) and the DE (Drawing Engine). Two engines. Parallel. Feeding off the primary ring. the way that works is genuinely so cool 😭

Because resource descriptors have moved to memory, the CE lets you prime the caches while the DE is updating register state β€” so that the resource descriptors will already be in cache when the draw is processed. obsessed with this kind of forward-thinking behaviour πŸ’…βœ¨

To pull this off, the userspace driver submits two IBs: one for the CE and one for the DE. And if there's a CE IB (which, fun fact, is called a CONST_IB), it will be put on the ring prior to the DE IB. order matters, bestie 🫢

And prior to SI? There was just a DE IB. simpler times, lowkey πŸ™ˆ


🌈 SEE ALSO 🌈

go check out the kernel file ./drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c β€” and while you're in there, the whole friend group:

they're all linked, they all slay, go read them πŸ¦‹πŸ’œ


that's the whole page bestie!! mwah πŸ’‹ this one lives in ./drivers/gpu/drm/amd/amdgpu and it's dated October 2026, filed under amdgpu_ib_schedule(9) β€” go off and schedule those IBs responsibly, ily πŸ’–πŸŽ€

πŸ“¦ where this page comes from