STRUCT EXYNOS5_DMC(9)

📦 version 7.3.1, in nixpkgs unstable

💖 struct exynos5_dmc(9) 💖

okay so bestie, welcome to the Kernel API Manual page for struct exynos5_dmc — the main character struct that describes the whole DMC device ✨ no cap, she's kind of a big deal.

🎀 NAME 🎀

struct exynos5_dmc — the main structure describing the DMC device. that's it, that's the vibe 💅

🌸 SYNOPSIS 🌸

here's the whole glow-up, copy-pasted with love (and zero edits, promise):

struct exynos5_dmc {
    struct device *dev;
    struct devfreq *df;
    struct devfreq_simple_ondemand_data gov_data;
    void __iomem *base_drexi0;
    void __iomem *base_drexi1;
    struct regmap *clk_regmap;
    struct mutex lock;
    unsigned long curr_rate;
    unsigned long curr_volt;
    struct dmc_opp_table *opp;
    int opp_count;
    u32 timings_arr_size;
    u32 *timing_row;
    u32 *timing_data;
    u32 *timing_power;
    const struct lpddr3_timings *timings;
    const struct lpddr3_min_tck *min_tck;
    u32 bypass_timing_row;
    u32 bypass_timing_data;
    u32 bypass_timing_power;
    struct regulator *vdd_mif;
    struct clk *fout_spll;
    struct clk *fout_bpll;
    struct clk *mout_spll;
    struct clk *mout_bpll;
    struct clk *mout_mclk_cdrex;
    struct clk *mout_mx_mspll_ccore;
    struct devfreq_event_dev **counter;
    int num_counters;
    u64 last_overflow_ts[2];
    unsigned long load;
    unsigned long total;
    bool in_irq_mode;
 };

🦋 Members 🦋

like, every field, explained. no member left behind fr fr 🫶

  • dev — the DMC device itself 👑
  • df — the devfreq device structure, handed back to you by the devfreq framework
  • gov_data — the configuration for the devfreq governor
  • base_drexi0 — DREX0 registers mapping
  • base_drexi1 — DREX1 registers mapping
  • clk_regmap — the regmap for the clock controller registers
  • lock — protects curr_rate and the frequency/voltage setting section 🔒 (do not skip the lock, bestie, i'm begging)
  • curr_rate — current frequency
  • curr_volt — current voltage
  • opp — the OPP table
  • opp_count — number of opp elements
  • timings_arr_size — number of timings elements
  • timing_row — values for the timing row register, for each OPP
  • timing_data — values for the timing data register, for each OPP
  • timing_power — values for the timing power register, for each OPP (the original page spells it "balues" and honestly? she's valid, we stan anyway 😭)
  • timings — DDR memory timings, straight from the device tree 🌳
  • min_tck — DDR memory minimum timing values, also from the device tree
  • bypass_timing_row — value for the timing row register for bypass timings
  • bypass_timing_data — value for the timing data register for bypass timings
  • bypass_timing_power — value for the timing power register for bypass timings
  • vdd_mif — the Memory interface regulator
  • fout_spll — clock: SPLL
  • fout_bpll — clock: BPLL
  • mout_spll — clock: mux SPLL
  • mout_bpll — clock: mux BPLL
  • mout_mclk_cdrex — clock: mux mclk_cdrex
  • mout_mx_mspll_ccore — clock: mux mx_mspll_ccore
  • counter — devfreq events
  • num_counters — number of counter elements
  • last_overflow_ts — time (in ns) of the last overflow of each DREX ⏱️
  • load — utilization in percents
  • total — total time between devfreq events
  • in_irq_mode — whether she's running in interrupt mode (true) or polling (false) 🔥

⭐ Description ⭐

so this is the main structure for the Dynamic Memory Controller, and she covers literally everything: clocks, memory regions, HW information, parameters, and the current operating mode. the whole package. main character energy, periodt 💜

🌈 SEE ALSO 🌈

go read these next, bestie, they all live in the Kernel file ./drivers/memory/samsung/exynos5422-dmc.c:

aaaand that's the page!! 🎀 mwah 💋 this diva comes to you from ./drivers/memory/samsung, dated October 2026 — go off, queen, see you in the next manpage 🦋✨

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