exynos5_dmc_...req_and_volt(9)

📦 version 7.3.1, in nixpkgs unstable

💅 exynos5_dmc_change_freq_and_volt(9) 💅

okay bestie, so this is a page from the Kernel API Manual, section 9 — it's the one about exynos5_dmc_change_freq_and_volt, and yes the header abbreviates it as exynos5_dmc_...req_and_volt(9) because apparently even kernel devs run out of screen width 😭. Anyway. Sit down, hydrate, let's go 🫶

✨ NAME ✨

exynos5_dmc_change_freq_and_volt — changes the voltage and the frequency of the DMC, and does it using the safe procedure (the whole point, no cap 🔥)

✨ SYNOPSIS ✨

int exynos5_dmc_change_freq_and_volt (struct exynos5_dmc *dmc , unsigned
long target_rate , unsigned long target_volt );

🌸 ARGUMENTS 🌸

  • dmc — the device whose frequency is about to get a whole new vibe. this is the thing we're changing 🎀
  • target_rate — the requested new frequency, aka the glow-up destination ✨
  • target_volt — the requested voltage that corresponds to that new frequency. they're a matching set, iykyk 💜

🦋 DESCRIPTION 🦋

okay so the DMC frequency change procedure takes a few steps, it's giving "getting ready" montage 💅

the main requirement is: you've gotta change the clock source in the clk mux for the time when the main clock PLL is locking. and the assumption here — the thing we're just trusting — is that the alternative clock source set as parent is stable. 🧚

that second parent's clock frequency is fixed at 400MHz, and it's named the 'bypass' clock. iconic name, honestly 👑

this requires alignment in the DRAM timing parameters for the new T-period. and there are, in fact, two bank sets for keeping DRAM timings: set 0 and set 1.

  • set 0 is used when the main clock source is chosen
  • the 2nd set of regs is used for the 'bypass' clock

switching between the two bank sets is part of the process. like, literally built in ✨

the voltage must also be aligned to the minimum required level. and there's this intermediate step where we switch to the 'bypass' parent clock source. > if the old voltage is lower, it requires an increase of the voltage level. so like, heads up — that's a real thing that has to happen ⚠️

the complexity of the voltage manipulation is hidden in a low level function (not our problem, bestie 🙈). and in this function there's a last alignment of the voltage level at the end. last step, final touch, periodt 💅

💖 SEE ALSO 💖

and that's the whole page, bestie, you ate that 🍓 this little beauty lives over in ./drivers/memory/samsung and it's dated October 2026, with the manual title being exynos5_dmc_...req_and_volt(9) — go forth and change those frequencies safely 💖✨🎀

📦 where this page comes from