exynos5_switch_timing_regs(9)

💅 exynos5_switch_timing_regs(9) 💅

okay bestie, welcome to the Kernel API Manual page for exynos5_switch_timing_regs(9) — manual name folded in right at the top like a little name tag 🫶. This is the function that changes the bank register set for DRAM timings, and it's lowkey a backstage-pass situation for the DRAM clock vibes ✨.

🌸 NAME 🌸

exynos5_switch_timing_regs — changes bank register set for DRAM timings 💖

✨ SYNOPSIS ✨

int exynos5_switch_timing_regs (struct exynos5_dmc *dmc , bool set );

🎀 ARGUMENTS 🎀

• dmc — the device that's about to get the new settings applied 🫶
• set — a boolean variable that passes the set value 💅

🦋 DESCRIPTION 🦋

Okay so this function changes the register set that holds the timing parameters. There are two register sets: 0 and 1 — not a crowd, just a duo 👯.

Register set 0 is used in normal operation when the clock is provided from the main PLL. Bank register set 1 is used when the main PLL frequency is going to be changed and the clock is taken from an alternative, stable source. This function switches between these banks according to the currently used clock source. Periodt. 💅

🌈 SEE ALSO 🌈

The whole squad is here, plus the kernel file that hosts the lore:

• Kernel file: ./drivers/memory/samsung/exynos5422-dmc.c
• struct dmc_opp_table(9)
• struct exynos5_dmc(9)
• find_target_freq_idx(9)
• exynos5_init_freq_table(9)
• exynos5_set_bypass_dram_timings(9)
• exynos5_dram_change_timings(9)
• exynos5_dmc_align_target_voltage(9)
• exynos5_dmc_align_bypass_voltage(9)
• exynos5_dmc_align_bypass_dram_timings(9)
• exynos5_dmc_switch_to_bypass_configuration(9)
• exynos5_dmc_change_freq_and_volt(9)
• exynos5_dmc_get_volt_freq(9)
• exynos5_dmc_target(9)
• exynos5_counters_get(9)
• exynos5_dmc_start_perf_events(9)
• exynos5_dmc_perf_events_calc(9)
• exynos5_dmc_perf_events_check(9)
• exynos5_dmc_enable_perf_events(9)
• exynos5_dmc_disable_perf_events(9)
• exynos5_dmc_get_status(9)
• exynos5_dmc_get_cur_freq(9)
• exynos5_dmc_align_init_freq(9)
• create_timings_aligned(9)
• of_get_dram_timings(9)
• exynos5_dmc_init_clks(9)
• exynos5_performance_counters_init(9)
• exynos5_dmc_set_pause_on_switching(9)
• exynos5_dmc_probe(9)
• exynos5_dmc_remove(9)

That's the whole page, bestie — the cute little footer says source/version ./drivers/memory/samsung and date October 2026. Bye, love you, go switch those timing regs responsibly 💖✨