sdma_v4_0_enable(9)

💅 sdma_v4_0_enable(9) — Kernel API Manual Energy ✨

okay bestie, welcome to the Kernel API Manual page for sdma_v4_0_enable(9) — we’re folding that manual name right in here because we’re cute like that. This is the kernel-side vibe check for the async DMA engines, and the signature is giving “one bool to rule them all” energy. 🫶

🌸 NAME 🌸

sdma_v4_0_enable — stop the async dma engines. That’s the official one-liner, and ngl it’s got main-character energy despite being a one-line summary. 💀

✨ SYNOPSIS ✨

void sdma_v4_0_enable (struct amdgpu_device *adev , bool enable );

This is literally the whole call, bestie: void, takes an amdgpu_device *adev, and a bool enable. No cap. 🎀

🦋 ARGUMENTS 🦋

• adev — amdgpu_device pointer. This is your device pointer, the little handle to the AMDGPU device.
• enable — enable/disable the DMA MEs. It’s a bool, and it’s here to say whether the DMA MEs get enabled or disabled.

💜 DESCRIPTION 💜

This function halts or unhalts the async dma engines — specifically on VEGA10. That’s it. That’s the whole description. It’s the on/off switch energy for those engines, and the (VEGA10) is important, so don’t come for me if you’re on some other chip. 😭

🌈 SEE ALSO 🌈

okay so the manpage points at the kernel file and a whole friend group of related sdma_v4_0_* functions. Gotta list every single one, because bestie we do not skip the boring parts. 💅

• Kernel file: ./drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
• sdma_v4_0_init_microcode(9)
• sdma_v4_0_ring_get_rptr(9)
• sdma_v4_0_ring_get_wptr(9)
• sdma_v4_0_ring_set_wptr(9)
• sdma_v4_0_page_ring_get_wptr(9)
• sdma_v4_0_page_ring_set_wptr(9)
• sdma_v4_0_ring_emit_ib(9)
• sdma_v4_0_ring_emit_hdp_flush(9)
• sdma_v4_0_ring_emit_fence(9)
• sdma_v4_0_gfx_enable(9)
• sdma_v4_0_rlc_stop(9)
• sdma_v4_0_page_stop(9)
• sdma_v4_0_ctx_switch_enable(9)
• sdma_v4_0_gfx_resume(9)
• sdma_v4_0_page_resume(9)
• sdma_v4_0_rlc_resume(9)
• sdma_v4_0_load_microcode(9)
• sdma_v4_0_start(9)
• sdma_v4_0_ring_test_ring(9)
• sdma_v4_0_ring_test_ib(9)
• sdma_v4_0_vm_copy_pte(9)
• sdma_v4_0_vm_write_pte(9)
• sdma_v4_0_vm_set_pte_pde(9)
• sdma_v4_0_ring_pad_ib(9)
• sdma_v4_0_ring_emit_pipeline_sync(9)
• sdma_v4_0_ring_emit_vm_flush(9)
• sdma_v4_0_emit_copy_buffer(9)
• sdma_v4_0_emit_fill_buffer(9)

cute sign-off time, bestie: this page comes from source/version ./drivers/gpu/drm/amd/amdgpu, dated October 2026, and the page is sdma_v4_0_enable(9). slay. 💖