devm_cxl_add_rch_dport(9)

💅 devm_cxl_add_rch_dport(9) — the kernel API manual, but make it make sense

okay bestie so this page lives in the Kernel API Manual (yes, that manual) and it's all about devm_cxl_add_rch_dport — say that five times fast, I dare you 😭 it's the function that appends RCH downstream port data to a cxl_port. That's the whole vibe. CXL core, RCH downstream ports, devm-managed. Slay.

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✨ SYNOPSIS ✨

struct cxl_dport * devm_cxl_add_rch_dport (struct cxl_port *port ,
struct device *dport_dev , int port_id , resource_size_t rcrb );

that's the signature, copy it exactly, don't come for me 🫶

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🎀 ARGUMENTS 🎀

• port — the cxl_port that references this dport. like, the port that's claiming this downstream port as its own, iykyk.
• dport_dev — the firmware or PCI device representing the dport. literally the device telling us "hi, I'm the downstream port 💁"
• port_id — the identifier for this dport in a decoder's target list. that's where it shows up, that's its little name tag.
• rcrb — the mandatory location of a Root Complex Register Block. mandatory!! not optional, not "if u feel like it", mandatory 🔥

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🦋 DESCRIPTION 🦋

so the actual description here is, and I quote the source of truth: See CXL 3.0 9.11.8 CXL Devices Attached to an RCH. that's it. that's the lore. go read the spec section, it's giving "the real documentation is the friends we made along the way" 😭📖

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🌈 SEE ALSO 🌈

bestie, the reading list is long and honestly iconic. here's every single one, no skips:

• Kernel file ./drivers/cxl/core/port.c
• cxl core(9)
• devm_cxl_add_port(9)
• devm_cxl_add_dport(9)
• cxl_add_ep(9)
• find_cxl_port_by_dport(9)
• find_cxl_port_by_uport(9)
• cxl_decoder_init(9)
• cxl_root_decoder_alloc(9)
• cxl_switch_decoder_alloc(9)
• cxl_endpoint_decoder_alloc(9)
• cxl_decoder_add_locked(9)
• cxl_decoder_add(9)
• __cxl_driver_register(9)
• cxl_endpoint_get_perf_coordinates(9)

like, go off, cross-reference section 👑 go read all of them, fr fr.

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ngl this one's short but it's mighty — the key takeaway is: rcrb is mandatory, and port_id shows up in a decoder's target list. don't forget it 💀

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and that's the whole page, bestie 💖 this gem comes out of ./drivers/cxl/core, dated October 2026, and if u ever need to find it again just yell devm_cxl_add_rch_dport(9) into the group chat and someone will pull it up 🎀✨