devm_cxl_add_port(9)

πŸ“¦ version 7.3.1, in nixpkgs unstable

πŸ’… devm_cxl_add_port(9) β€” from the Kernel API Manual, bestie ✨

okay so picture this: it's giving kernel API manual energy, the header says devm_cxl_add_port(9), and the whole vibe is "register a cxl_port in the CXL memory decode hierarchy." That's it, that's the plot πŸŽ€ no cap, that's the NAME right there.

Basically this function is the main character of port registration β€” it's out here putting a cxl_port into the CXL memory decode hierarchy, with all the devm-managed housekeeping handled for you. Obsessed 🫢


✨ SYNOPSIS ✨

struct cxl_port * devm_cxl_add_port (struct device *host , struct device *uport_dev , resource_size_t component_reg_phys , struct cxl_dport *parent_dport );

yeah she takes four arguments, and every single one matters, so let's go πŸ’…


🌸 ARGUMENTS 🌸

  • host β€” the host device for devm operations. like, this is the device that owns all the devm cleanup magic ✨
  • uport_dev β€” the "physical" device implementing this upstream port πŸ¦‹ (yes the quotes around physical are in the original, iykyk)
  • component_reg_phys β€” (optional), for configurable cxl_port instances πŸ”₯
  • parent_dport β€” the next hop up in the CXL memory decode hierarchy, aka who you're reporting to πŸ’€

πŸ‘‘ SEE ALSO πŸ‘‘

Kernel file ./drivers/cxl/core/port.c cxl core(9), plus the whole friend group of related calls β€” literally the entire group chat, not me listing all of them πŸ™ˆ


real talk: component_reg_phys is straight-up marked (optional) in the original, so don't come for me if you skip it for the configurable cxl_port instances πŸ’–

okay that's the whole page, no crumbs left 🌈 and for the cute sign-off: this little icon lives in the source tree at ./drivers/cxl/core, it's dated October 2026, and the footer-repping title is devm_cxl_add_port(9) β€” periodt πŸ’…βœ¨πŸ“

πŸ“¦ where this page comes from