CXL CORE(9)

🌸 cxl core 🌸

okay bestie, this is the Kernel API Manual page for cxl core, and it's lowkey iconic. The CXL core provides a set of interfaces that can be consumed by CXL aware drivers. Those interfaces allow for creation, modification, and destruction of regions, memory devices, ports, and decoders. Slay. 💅

CXL aware drivers must register with the CXL core via these interfaces in order to be able to participate in cross-device interleave coordination. No cap — that's the whole point. The CXL core also establishes and maintains the bridge to the nvdimm subsystem. 🫶

CXL core introduces a sysfs hierarchy to control the devices that are instantiated by the core. The way it just organizes the whole vibe? Obsessed. ✨

🌈 SEE ALSO 🌈

• Kernel file ./drivers/cxl/core/port.c
• devm_cxl_add_port(9)
• devm_cxl_add_dport(9)
• devm_cxl_add_rch_dport(9)
• cxl_add_ep(9)
• find_cxl_port_by_dport(9)
• find_cxl_port_by_uport(9)
• cxl_decoder_init(9)
• cxl_root_decoder_alloc(9)
• cxl_switch_decoder_alloc(9)
• cxl_endpoint_decoder_alloc(9)
• cxl_decoder_add_locked(9)
• cxl_decoder_add(9)
• __cxl_driver_register(9)
• cxl_endpoint_get_perf_coordinates(9)

That's the whole guest list, bestie — every single SEE ALSO reference is right there, exactly as the page gives it. 🎀

okay that's the page! Source/version path: ./drivers/cxl/core · date: October 2026 · manual entry: cxl core(9). Byeee, ily, go read those functions 🦋💖🔥