VASY(1)

💅 VASY(1) — the CAO-VLSI girlies' manual, but make it make sense ✨

okay so bestie, welcome to VASY — short for VHDL Analyzer for Synthesis — straight out of the CAO-VLSI Reference Manual. she's iconic, she's a little dramatic, and she's gonna analyze your VHDL so hard. let's get into it 🫶

🌈 ORIGIN

this software belongs to the ALLIANCE CAD SYSTEM, developed by the ASIM team at the LIP6 laboratory of Université Pierre et Marie CURIE, in Paris, France. très chic, no cap 💖

• Web : http://asim.lip6.fr/recherche/alliance/
• E-mail : alliance-users@asim.lip6.fr

✨ SYNOPSIS ✨

vasy [-VpavsoipSHL] [-C num] [-E num] [-I format] [-P file] filename
[outname]

that's the whole vibe check right there. filename is your input, outname is the glow-up she gives back 💅

🦋 DESCRIPTION

VASY is a hierarchical VHDL Analyzer for Synthesis. periodt. she performs a semantic analysis of a VHDL RTL description called filename, using a VHDL subset that is much more extended than the Alliance one (peep vasy(5) for the deets, iykyk), and she identifies with precision all the memorizing elements and tristate buffers. literally so precise it's giving main character energy 👑

during her analysis, VASY expands generic parameters, executes generic map and generate statements, and also unrolls static FOR loops. she does the boring stuff so you don't have to, fr fr 🧚

and at the end? at the end she drives an equivalent description outname — in Verilog or VHDL format — accepted by most of synthesis tools. slay. ate. left no crumbs. 🔥

🎀 ENVIRONMENT VARIABLES 🎀

• MBK_WORK_LIB(1) — indicates the path to the read/write directory for the session. that's her little workspace, her little room, her little safe space 💜

💅 OPTIONS 💅

okay this is the part where we read the whole menu, no skipping, we don't do that here 💖

• -V — Verbose mode on. each step of the analysis is displayed on the standard output. she's narrating her life and honestly? let her 🗣️
• -v — Drives an equivalent description in Verilog format. going the Verilog route bestie 💫
• -a — Drives an equivalent description in Alliance VHDL format vbe(5) and/or vst(5). heads up tho: with this option, all arithmetic operators are expanded in an equivalent set of boolean expressions, because these operators don't belong to the Alliance VHDL subset. she's translating, not copying 😭
• -s — Drives an equivalent VHDL description (with the extention .vhd) accepted by most of industrial synthesis tools. yes the original says "extention", we're keeping it, be nice 🎀
• -S — Uses Std_logic instead of Bit (taken into account only with option -s). only valid with the -s girlies ✨
• -i — Drives initial signal values (taken into account only with option -s). again, -s only, don't @ me 💅
• -I format — Specifies the VHDL input format such as Alliance VHDL format vbe(5), vst(5) or industrial VHDL format vhd or vhdl. tell her what dialect you're speaking 🦋
• -H — In a structural description, all model of instances are recursively analyzed. (By default VASY analyzes only models with generic parameters) The leaves cells are defined by a file called CATAL (see catal(5) for details). she's going deep, recursive, obsessed 🔍
• -o — Authorizes to overwrite existing files. she'll bulldoze your old files, but only if you say please 🙈
• -p — Adds power supply connectors (vdd and vss). Useful option to enter in Alliance. powering up the whole fit ⚡
• -C num — When the size of the adder is greater or equal to num a Carry Look Ahead adder is generated, instead of a Ripple Carry adder. (taken into account only with option -a). fancy adder upgrade, -a only 👑
• -E num — Comparators are expanded in an equivalent set of boolean expressions, when their size is greater than num (taken into account only with option -a). again: -a only, no exceptions 🌸
• -L — A file .lax (see lax(5) for details) is generated. This file contains the list of all signals that must be kept during the synthesis step, using boom (see boom(1) for details). (taken into account only with option -a). she's making a little keep-list, -a only 🎀
• -P file — Specifies a 'file.pkg' containing a list of logical and physical package name:

# Example
work.constants.all  : pkg_constants
work.components.all : pkg_components

🌟 SEE ALSO 🌟

vasy(5), vbe(5), vhdl(5), catal(5). lax(5). asimut(1), boom(1), MBK_WORK_LIB(1). MBK_CATA_LIB(1). MBK_CATAL_NAME(1). go read them, they're all besties 🫶

💀 BUG REPORT 💀

This tool is under development at the ASIM department of the LIP6 laboratory.

We need your feedback to improve documentation and tools.

so like… tell them if something's weird!! they're literally asking!! be the helpful friend 🌸

no cap, this tool is under development — so if something's giving bug, that's why, and your feedback is genuinely the moment 💖

and that's the whole page bestie ily, go synthesize something iconic 💜✨

ASIM/LIP6 — November 26, 1999 — VASY(1) 🎀 (that's the source, the version, and the date, all tucked into one cute little sign-off — mwah 💋)