zl3073x_dpl...e_phase_step(9)

📦 version 7.3.1, in nixpkgs unstable

💅 zl3073x_dpll_ptp_adjtime_phase_step — like, the whole glow-up 💅

okay so bestie, welcome to the Kernel API Manual ✨ this is the page for zl3073x_dpll_ptp_adjtime_phase_step(9) and honestly? it's giving "tiny function, big responsibilities" 🎀

✨ NAME ✨

zl3073x_dpll_ptp_adjtime_phase_step — adjust sub-second time via phase step 🕰️💫

🌸 SYNOPSIS 🌸

int zl3073x_dpll_ptp_adjtime_phase_step(struct zl3073x_dpll *zldpll, s64 delta);

🦋 ARGUMENTS 🦋

  • zldpll — the DPLL channel, aka the main character of this whole operation 👑
  • delta — the time adjustment in nanoseconds. and listen, it must be within (-NSEC_PER_SEC, NSEC_PER_SEC) — no cap, that's a hard boundary, do not test it 🙈

💖 DESCRIPTION 💖

So here's the vibe: this uses the output phase step mechanism with tod_step=1 so it can adjust both the output clock phase and the ToD counter at the same time. the way that keeps outputs and ToD coherent? iconic. 🤝✨ Only valid for NCO, just so you know.

Outputs get grouped by synthesizer, because the phase step value lives in synthesizer clock cycles ⏱️. The first synth group with enabled outputs uses tod_step to adjust both the outputs and the ToD counter. The remaining groups step outputs only, periodt. 💅

And if no synth has enabled outputs? the ToD counter gets stepped all by itself using an empty output mask — fr fr, the FW uses the first enabled synth's period for the conversion. 🫶

🔥 RETURN 🔥

  • 0 — success 🎉 (or partial success, if a later synth group failed after the first one was already stepped — yeah, that's a thing 😭)
  • -EOPNOTSUPP — no synths available, bestie 💀
  • negative — error 🙈

⭐ SEE ALSO ⭐

Kernel file ./drivers/dpll/zl3073x/dpll.c, plus all of these legends:

and that's the whole page, bestie 🫶 this lil gem lives in ./drivers/dpll/zl3073x, dated October 2026 — go read it, slay, bye 💜🧚‍♀️

📦 where this page comes from