vcn_v5_0_0_sw_fini(9)
πΈ vcn_v5_0_0_sw_fini(9) β Kernel API Manual πΈ
okay bestie, welcome to the Kernel API Manual page for vcn_v5_0_0_sw_fini π
this is the sw fini moment for the VCN block, and yes it's giving βwe're wrapping up the software sideβ energy β¨
β¨ NAME β¨
vcn_v5_0_0_sw_fini β sw fini for VCN block π
π SYNOPSIS π
int vcn_v5_0_0_sw_fini (struct amdgpu_ip_block *ip_block );
π ARGUMENTS π
ip_blockβ pointer to theamdgpu_ip_blockfor this hw instance π«Ά that's the one and only arg, bestie.
π¦ DESCRIPTION π¦
okay so this is literally the VCN suspend and free up sw allocation step π it suspends VCN and frees up the sw allocation, periodt. no cap, that's the whole vibe: software fini for the VCN block, doing its teardown thing so everything can wrap up cleanly π§
π SEE ALSO π
kernel file: ./drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c π
the whole squad, fr fr:
vcn_v5_0_0_early_init(9)vcn_v5_0_0_sw_init(9)vcn_v5_0_0_hw_init(9)vcn_v5_0_0_hw_fini(9)vcn_v5_0_0_suspend(9)vcn_v5_0_0_resume(9)vcn_v5_0_0_mc_resume(9)vcn_v5_0_0_mc_resume_dpg_mode(9)vcn_v5_0_0_disable_static_power_gating(9)vcn_v5_0_0_enable_static_power_gating(9)vcn_v5_0_0_disable_clock_gating(9)vcn_v5_0_0_disable_clock_gating_dpg_mode(9)vcn_v5_0_0_enable_clock_gating(9)vcn_v5_0_0_start_dpg_mode(9)vcn_v5_0_0_set_mmhub_eco_sec_level(9)vcn_v5_0_0_start(9)vcn_v5_0_0_stop_dpg_mode(9)vcn_v5_0_0_stop(9)vcn_v5_0_0_pause_dpg_mode(9)vcn_v5_0_0_unified_ring_get_rptr(9)vcn_v5_0_0_unified_ring_get_wptr(9)vcn_v5_0_0_unified_ring_set_wptr(9)vcn_v5_0_0_set_unified_ring_funcs(9)vcn_v5_0_0_is_idle(9)vcn_v5_0_0_wait_for_idle(9)vcn_v5_0_0_set_clockgating_state(9)vcn_v5_0_0_process_interrupt(9)vcn_v5_0_0_set_irq_funcs(9)
mwah π bye bestie β source/version ./drivers/gpu/drm/amd/amdgpu, October 2026 β¨π
π¦ where this page comes from
- nixpkgs unstable: linux-manual 7.3.1
- π girlified by deepseek-ai/DeepSeek-V4.1-Flash-1017 on : a language model's rewrite of the original, under its terms