STRUCT XILINX_DMA_DEVICE(9)

📦 version 7.3.1, in nixpkgs unstable

💅 struct xilinx_dma_device — the kernel API manual moment 🎀

okay so bestie, welcome to the glow-up of struct xilinx_dma_device(9) ✨ this is from the Kernel API Manual and honestly it's giving "main character energy" for the Xilinx DMA driver. stay with me, it's literally just one struct and a whole lot of friends in SEE ALSO 💖

🌸 NAME 🌸

struct xilinx_dma_device — the DMA device structure, no cap 🦋

✨ SYNOPSIS ✨

here's the whole thing, copied exactly because we do not play with code around here 🫶

struct xilinx_dma_device {
    void __iomem *regs;
    struct device *dev;
    struct dma_device common;
    struct xilinx_dma_chan *chan[XILINX_MCDMA_MAX_CHANS_PER_DEVICE];
    u32 flush_on_fsync;
    bool ext_addr;
    struct platform_device  *pdev;
    const struct xilinx_dma_config *dma_config;
    struct clk *axi_clk;
    struct clk *tx_clk;
    struct clk *txs_clk;
    struct clk *rx_clk;
    struct clk *rxs_clk;
    u32 s2mm_chan_id;
    u32 mm2s_chan_id;
    u32 max_buffer_len;
    bool has_axistream_connected;
 };

🧚 Members 🧚

okay so this is the part where we go member by member and it's lowkey the best part 💅

  • regs — the I/O mapped base address. like, where it all lives in memory ✨
  • dev — the Device Structure. the whole device vibe check 🎀
  • common — the DMA device structure. the shared, communal one 🌈
  • chan — the driver specific DMA channel. type is struct xilinx_dma_chan * and it's an array of XILINX_MCDMA_MAX_CHANS_PER_DEVICE, iykyk 💜
  • flush_on_fsync — Flush on frame sync. a u32, doing exactly what it says 🦋
  • ext_addr — indicates 64 bit addressing is supported by the dma device. icon behavior ngl 👑
  • pdev — Platform device structure pointer. struct platform_device *, slay 🌸
  • dma_config — the DMA config structure. it's a const struct xilinx_dma_config * 🎀
  • axi_clk — DMA Axi4-lite interace clock. (yes, "interace" — that's the original spelling, we don't touch it 🙈)
  • tx_clk — DMA mm2s clock ⏰
  • txs_clk — DMA mm2s stream clock. the stream-y one 💫
  • rx_clk — DMA s2mm clock ⏰
  • rxs_clk — DMA s2mm stream clock. also stream-y 💫
  • s2mm_chan_id — DMA s2mm channel identifier. a u32 🔥
  • mm2s_chan_id — DMA mm2s channel identifier. also a u32 🔥
  • max_buffer_len — Max buffer length. u32. don't exceed it, bestie 😭
  • has_axistream_connected — AXI DMA connected to AXI Stream IP. a bool, and yes it's a whole mood 🧚

👑 SEE ALSO 👑

buckle up, this list is long and it ate 💀 every single one, in order, fr fr:

Kernel file ./drivers/dma/xilinx/xilinx_dma.c struct xilinx_vdma_desc_hw(9), struct xilinx_axidma_desc_hw(9), struct xilinx_aximcdma_desc_hw(9), struct xilinx_cdma_desc_hw(9), struct xilinx_vdma_tx_segment(9), struct xilinx_axidma_tx_segment(9), struct xilinx_aximcdma_tx_segment(9), struct xilinx_cdma_tx_segment(9), struct xilinx_dma_tx_descriptor(9), struct xilinx_dma_chan(9), enum xdma_ip_type(9), vdma_desc_write_64(9), xilinx_dma_get_metadata_ptr(9), xilinx_vdma_alloc_tx_segment(9), xilinx_cdma_alloc_tx_segment(9), xilinx_axidma_alloc_tx_segment(9), xilinx_aximcdma_alloc_tx_segment(9), xilinx_dma_free_tx_segment(9), xilinx_mcdma_free_tx_segment(9), xilinx_cdma_free_tx_segment(9), xilinx_vdma_free_tx_segment(9), xilinx_dma_alloc_tx_descriptor(9), xilinx_dma_free_tx_descriptor(9), xilinx_dma_free_desc_list(9), xilinx_dma_free_descriptors(9), xilinx_dma_free_chan_resources(9), xilinx_dma_get_residue(9), xilinx_dma_chan_handle_cyclic(9), xilinx_dma_chan_desc_cleanup(9), xilinx_dma_do_tasklet(9), xilinx_dma_alloc_chan_resources(9), xilinx_dma_calc_copysize(9), xilinx_dma_tx_status(9), xilinx_dma_stop_transfer(9), xilinx_cdma_stop_transfer(9), xilinx_dma_start(9), xilinx_vdma_start_transfer(9), xilinx_cdma_start_transfer(9), xilinx_dma_start_transfer(9), xilinx_mcdma_start_transfer(9), xilinx_dma_issue_pending(9), xilinx_dma_device_config(9), xilinx_dma_complete_descriptor(9), xilinx_dma_reset(9), xilinx_dma_chan_reset(9), xilinx_mcdma_irq_handler(9), xilinx_dma_irq_handler(9), append_desc_queue(9), xilinx_dma_tx_submit(9), xilinx_vdma_dma_prep_interleaved(9), xilinx_cdma_prep_memcpy(9), xilinx_dma_prep_peripheral_dma_vec(9), xilinx_dma_prep_slave_sg(9), xilinx_dma_prep_dma_cyclic(9), xilinx_mcdma_prep_slave_sg(9), xilinx_dma_terminate_all(9), xilinx_vdma_channel_set_config(9), xilinx_dma_chan_remove(9), xilinx_dma_chan_probe(9), xilinx_dma_child_probe(9), of_dma_xilinx_xlate(9), xilinx_dma_probe(9), xilinx_dma_remove(9)

bestie that's a lot of references and every single one is staying, periodt 💅

🎀 cute little sign-off 🎀

this whole page comes from ./drivers/dma/xilinx, dated October 2026, and it's filed under struct xilinx_dma_device(9) in the Kernel API Manual. obsessed. go read the source, ily, bye 🫶💖✨

📦 where this page comes from