STRUCT XILINX_DMA_CHAN(9)

📦 version 7.3.1, in nixpkgs unstable

💅 struct xilinx_dma_chan(9) 💅

okay bestie, welcome to the Kernel API Manual ✨ this one's all about struct xilinx_dma_chan and honestly? it's kind of a whole vibe. strap in 🎀

🌸 NAME 🌸

struct xilinx_dma_chan — the driver-specific DMA channel structure. like, the channel's personality, its whole little world 💖

✨ SYNOPSIS ✨

struct xilinx_dma_chan {
    struct xilinx_dma_device *xdev;
    u32 ctrl_offset;
    u32 desc_offset;
    spinlock_t lock;
    struct list_head pending_list;
    struct list_head active_list;
    struct list_head done_list;
    struct list_head free_seg_list;
    struct dma_chan common;
    struct dma_pool *desc_pool;
    struct device *dev;
    int irq;
    int id;
    enum dma_transfer_direction direction;
    int num_frms;
    bool has_sg;
    bool cyclic;
    bool genlock;
    bool err;
    bool idle;
    bool terminating;
    struct tasklet_struct tasklet;
    struct xilinx_vdma_config config;
    bool flush_on_fsync;
    u32 desc_pendingcount;
    bool ext_addr;
    u32 desc_submitcount;
    struct xilinx_axidma_tx_segment *seg_v;
    struct xilinx_aximcdma_tx_segment *seg_mv;
    dma_addr_t seg_p;
    struct xilinx_axidma_tx_segment *cyclic_seg_v;
    dma_addr_t cyclic_seg_p;
    void (*start_transfer)(struct xilinx_dma_chan *chan);
    int (*stop_transfer)(struct xilinx_dma_chan *chan);
    u16 tdest;
    bool has_vflip;
    u8 irq_delay;
 };

🦋 Members 🦋

  • xdev — the driver-specific device structure. the parent, the origin story 👑
  • ctrl_offset — control registers offset 📍
  • desc_offset — TX descriptor registers offset 📍
  • lock — descriptor operation lock. no cap, everybody needs one 🔒
  • pending_list — descriptors that are waiting. they're in the queue, bestie ⏳
  • active_list — descriptors that are ready to submit 🔥
  • done_list — complete descriptors. ate and left no crumbs ✅
  • free_seg_list — free descriptors, just chilling 🍓
  • common — the DMA common channel 🤝
  • desc_pool — the descriptors pool 🏊
  • dev — the dma device
  • irq — the channel IRQ ⚡
  • id — the channel ID 🏷️
  • direction — transfer direction 🧭
  • num_frms — number of frames 🎞️
  • has_sg — does it support scatter transfers 🌪️
  • cyclic — check for cyclic transfers. it goes around and around, main character energy 🔄
  • genlock — support genlock mode 🔗
  • err — the channel has errors 😭
  • idle — check for channel idle 😴
  • terminating — check for channel being synchronized by user 🙈
  • tasklet — cleanup work after irq 🧹
  • config — device configuration info ⚙️
  • flush_on_fsync — flush on Frame sync 🚿
  • desc_pendingcount — descriptor pending count 🔢
  • ext_addr — indicates 64 bit addressing is supported by dma channel 💅
  • desc_submitcount — descriptor h/w submitted count 🔢
  • seg_v — statically allocated segments base 🧱
  • seg_mv — statically allocated segments base for MCDMA 🧱
  • seg_p — physical allocated segments base 🧱
  • cyclic_seg_v — statically allocated segment base for cyclic transfers 🔁
  • cyclic_seg_p — physical allocated segments base for cyclic dma 🔁
  • start_transfer — differentiate b/w DMA IP's transfer. yes bestie, differentiate b/w, that's literally what the page says 💫
  • stop_transfer — differentiate b/w DMA IP's quiesce 🛑
  • tdest — TDEST value for mcdma 🎯
  • has_vflip — S2MM vertical flip 🙃
  • irq_delay — interrupt delay timeout ⏰

💜 SEE ALSO 💜

the kernel file ./drivers/dma/xilinx/xilinx_dma.c struct, plus this entire friend group of structs and functions — go say hi, iykyk 🫶

and that's the whole page, bestie 🫶 sourced fresh from ./drivers/dma/xilinx and dated October 2026 — go forth and slay your DMA channels ✨💅🎀

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