sdma_v5_0_enable(9)

💅 NAME 💅

okay so bestie, welcome to sdma_v5_0_enable(9) from the Kernel API Manual ✨ The official NAME tea is: stop the async dma engines. That’s the exact phrase, no edits, periodt 💅

✨ SYNOPSIS ✨

void sdma_v5_0_enable (struct amdgpu_device *adev , bool enable );

It’s giving tiny toggle-function energy: void, two arguments, no return value, no drama 🎀

🎀 ARGUMENTS 🎀

• adev — an amdgpu_device pointer. That’s the device context, bestie 🫶
• enable — enable/disable the DMA MEs. Literally the on/off vibe for the DMA MEs 💖

🦋 DESCRIPTION 🦋

Halt or unhalt the async dma engines (NAVI10). That’s the whole assignment: halt/unhalt, async dma engines, NAVI10, no cap 🌸

🌈 SEE ALSO 🌈

Kernel file: ./drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

• sdma_v5_0_init_microcode(9)
• sdma_v5_0_ring_get_rptr(9)
• sdma_v5_0_ring_get_wptr(9)
• sdma_v5_0_ring_set_wptr(9)
• sdma_v5_0_ring_emit_ib(9)
• sdma_v5_0_ring_emit_mem_sync(9)
• sdma_v5_0_ring_emit_hdp_flush(9)
• sdma_v5_0_ring_emit_fence(9)
• sdma_v5_0_gfx_stop(9)
• sdma_v5_0_rlc_stop(9)
• sdma_v5_0_ctx_switch_enable(9)
• sdma_v5_0_gfx_resume_instance(9)
• sdma_v5_0_gfx_resume(9)
• sdma_v5_0_rlc_resume(9)
• sdma_v5_0_load_microcode(9)
• sdma_v5_0_start(9)
• sdma_v5_0_ring_test_ring(9)
• sdma_v5_0_ring_test_ib(9)
• sdma_v5_0_vm_copy_pte(9)
• sdma_v5_0_vm_write_pte(9)
• sdma_v5_0_vm_set_pte_pde(9)
• sdma_v5_0_ring_pad_ib(9)
• sdma_v5_0_ring_emit_pipeline_sync(9)
• sdma_v5_0_ring_emit_vm_flush(9)
• sdma_v5_0_emit_copy_buffer(9)
• sdma_v5_0_emit_fill_buffer(9)

kisses bestie, this page is signed off from the ./drivers/gpu/drm/amd/amdgpu source corner, living in the Kernel API Manual, dated October 2026, and answering to sdma_v5_0_enable(9) 💖🫶✨