dce_v8_0_pick_pll(9)

📦 version 7.3.1, in nixpkgs unstable

💅 dce_v8_0_pick_pll(9) — the kernel API manual, bestie edition 🎀

okay so this is a page from the Kernel API Manual (yes, the actual kernel, we're fancy now) and it's all about one little function that's lowkey the matchmaker of your display pipeline. let's get into it 💖

✨ NAME ✨

dce_v8_0_pick_pll — allocate a PPLL for use by the crtc. that's it, that's the whole job. it finds a PLL and hands it over. king behavior honestly 👑

🌸 SYNOPSIS 🌸

u32 dce_v8_0_pick_pll (struct drm_crtc *crtc );

one arg, returns a u32. simple. clean. no notes. ✨

🦋 ARGUMENTS 🦋

  • crtc — the drm crtc. that's the whole description, bestie, the original said "drm crtc" and we're not gonna invent lore that isn't there 🙈 this is the crtc you're trying to find a PLL for.

💜 DESCRIPTION 💜

so here's the tea ☕ — this function returns the PPLL (that's the Pixel PLL, for anyone keeping score) that the crtc should use. and the rules for who gets which PLL are genuinely kind of interesting:

  • for DP monitors, a single PPLL can be used for all DP crtcs/encoders. one PLL, many friends. sharing is caring 🫶
  • for non-DP monitors, a dedicated PPLL must be used. no sharing, no borrowing, this one's yours and yours alone 💅

now for the edge cases, and listen up because these matter:

  • if a particular board has an external DP PLL, return ATOM_PPLL_INVALID — that skips PLL programming entirely, because hello? there's literally no need to program the PLL itself when the board already handles it 😌
  • if we are not able to allocate a PLL, return ATOM_PPLL_INVALID too — this skips PLL programming so we don't mess up an existing monitor. like, do no harm, y'know? 🫶
ngl the ATOM_PPLL_INVALID return shows up in two very different situations — external DP PLL and allocation failure — so don't assume "invalid" means "something broke". sometimes it means "not needed", sometimes it means "couldn't get one", and both times the answer is: skip the programming. 😭

🔥 Asic specific PLL information

the deets change depending on your chip, so here's the breakdown:

⭐ DCE 8.x KB/KV

  • PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) CI
  • PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC

so on KB/KV you've got the full trio PPLL0, PPLL1, PPLL2 doing UNIPHY duty and DAC duty, while the CI situation is just PPLL1 and PPLL2 on UNIPHY. iconic lineup honestly 🌈

👑 SEE ALSO 👑

the source lives here, in the kernel file ./drivers/gpu/drm/amd/amdgpu/dce_v8_0.c — go read it, it's giving main character energy 🧚

and here's the whole friend group, fr fr:

and that's the page!! 🎀 this little beauty comes to you from ./drivers/gpu/drm/amd/amdgpu, dated October 2026 — go forth and pick your PLLs responsibly, bestie 💖✨

📦 where this page comes from