amdgpu_dm_p...fx6_tile_idx(9)

📦 version 7.3.1, in nixpkgs unstable

💅 amdgpu_dm_plane_get_gfx6_tile_idx(9) 💅

okay so bestie, welcome to the Kernel API Manual ✨ — this one's about picking a tile mode index on GFX6-8, and honestly it's giving very niche-but-iconic energy 🎀

🌸 NAME 🌸

amdgpu_dm_plane_get_gfx6_tile_idx — Get tile mode index on GFX6-8 🦋

✨ SYNOPSIS ✨

u32 amdgpu_dm_plane_get_gfx6_tile_idx (const struct amdgpu_device *adev
, const u32 bpp , const enum array_mode_values arr );

like, that's the whole signature, no cap 💅

🫶 ARGUMENTS 🫶

  • adev — amdgpu_device pointer 👑 (the device, the main character of the arg list fr)
  • bpp — bits per pixel in the image 🌈
  • arr — array mode (aka. tile mode) of the image layout 🎀

🔥 DESCRIPTION 🔥

So what it actually does: it selects which tiling mode from the table is suitable for the given bits per pixel using the given array mode — assuming the displayable micro tile mode is the one being used. periodt 💅

On GFX6-8, the GFX block can only use pre-programmed tiling modes from GB_TILE_MODEn registers, and those registers are programmed by the kernel according to the tiling mode table 📋✨

⚠️ Bestie, listen: the tiling table is uAPI and userspace relies on specific modes being present at specific indices. Do not go messing with the ordering, iykyk 😭

See SiLib::HwlSetupTileInfo and CiLib::HwlSetupTileInfo in addrlib 🔍

💖 SEE ALSO 💖

aaaand that's the page, bestie 🫶 this icon was brought to you by the source at ./drivers/gpu/drm/amd/display/..., dated October 2026, in the amdgpu_dm_p...fx6_tile_idx(9) era 💜 go forth and tile responsibly ✨💅

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