amdgpu_dm_pl...7_tile_split(9)

💅 amdgpu_dm_plane_calc_gfx7_tile_split(9)

okay so bestie, you found it — this is the kernel API manual page for amdgpu_dm_plane_calc_gfx7_tile_split(9), straight out of section 9 of the Kernel API Manual. it's giving very niche, very AMD display driver, and honestly? kind of iconic. let's get into it 🎀

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✨ NAME ✨

amdgpu_dm_plane_calc_gfx7_tile_split — Calculate tile split on GFX7-8 🧮

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🌸 SYNOPSIS 🌸

u32 amdgpu_dm_plane_calc_gfx7_tile_split (const struct amdgpu_device
*adev , const u32 bpp , const u32 gb_tile_mode );

literally that's the whole signature, no cap. it returns a u32, so you already know a number is coming back at you. 💫

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🦋 ARGUMENTS 🦋

• adev — amdgpu_device pointer. the main character of the whole amdgpu universe, fr.
• bpp — bits per pixel in the image 🖼️
• gb_tile_mode — the GB_TILE_MODEn register value for the current tiling mode. yes, the actual register value, not a vibe. 👑

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💜 DESCRIPTION 💜

So what does it actually do? it calculates the real, actual tile split value on GFX7-8 — and it does that assuming 2D_TILED_THIN1 array mode with a non-depth micro tile mode. very specific, very demure. ✨

On GFX7-8, SAMPLE_SPLIT holds a factor, and you calculate the actual tile split bytes from that factor. meanwhile the TILE_SPLIT field is only used for the depth micro tile mode — so don't go using it for anything else, bestie, that's not what it's for. 🙈

if you want the receipts, check CiLib::HwlComputeMacroModeIndex in addrlib. that's where the logic lives, iykyk. 📚

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🔥 SEE ALSO 🔥

• Kernel file ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c — the whole file, go read it 💀
• amdgpu_dm_plane_get_gfx6_tile_idx(9)
• amdgpu_dm_plane_get_gfx7_macro_tile_idx(9)
• amdgpu_dm_plane_calc_gfx6_mod(9)
• amdgpu_dm_plane_gfx6_format_mod_supported(9)
• amdgpu_dm_plane_add_gfx6_modifiers(9)

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and that's the page!! 🫶 source is ./drivers/gpu/drm/amd/display/..., dated October 2026, and it's amdgpu_dm_pl...7_tile_split(9) all the way down. slay, go calc some tile splits 💅💖