amdgpu_dm_pl...x6_modifiers(9)

πŸ“¦ version 7.3.1, in nixpkgs unstable

πŸŽ€ amdgpu_dm_plane_add_gfx6_modifiers πŸ’…

okay bestie, so this one lives in the Kernel API Manual (section 9, the kernel-api girlies ✨) and the page title got chopped all cute and dramatic into amdgpu_dm_pl...x6_modifiers(9) β€” but the actual function is amdgpu_dm_plane_add_gfx6_modifiers, and she is literally the one exposing modifiers for GFX6-8. no cap. πŸ‘‘


✨ NAME ✨

amdgpu_dm_plane_add_gfx6_modifiers β€” Expose modifiers for GFX6-8 πŸ¦‹


🌸 SYNOPSIS 🌸

void amdgpu_dm_plane_add_gfx6_modifiers (const struct amdgpu_device *adev , u64 **mods , u64 *size , u64 *capacity );

like… four args, one void return, zero drama. periodt. πŸ’…


πŸ’– ARGUMENTS πŸ’–

  • adev β€” amdgpu_device pointer 🫢 (yes bestie, the device)
  • mods β€” Pointer to array of format modifiers ✨
  • size β€” Pointer to size of the array πŸŽ€
  • capacity β€” Pointer to capacity of the array 🌸
ngl, that's three separate pointers into the same array-ish situation. keep your eyes on them, queen. πŸ‘€

πŸ”₯ DESCRIPTION πŸ”₯

So here's the vibe: she calculates a DRM format modifier for macro tiled modes, for each supported bits per pixel value. every single one. she's thorough like that. πŸ’…

And because she's not about to be out here duplicating herself, she uses de-duplication β€” because on some GPUs it may happen that different bpp results in the exact same macro tiling mode, depending on the tiling table. 😭 like, same fit, different number. so she de-dupes. iconic behavior honestly.

She also exposes a micro tiled only mode. is it the most optimal? no bestie, it's less optimal. but is it supported? yes. and that's what matters. 🫢✨


🌈 SEE ALSO 🌈


needed, right? anyway bestie β€” this page came from ./drivers/gpu/drm/amd/display/... and it's dated October 2026, same as the footer on the original, so jot that down and go read the source, mwah πŸ’‹πŸ’– slay, you've got this πŸ§šβ€β™€οΈβœ¨

πŸ“¦ where this page comes from