__wrpll_update_parent_rate(9)

✨ __wrpll_update_parent_rate ✨

okay bestie, so this is a kernel API manual page — __wrpll_update_parent_rate(9), from the Kernel API Manual — and it's literally about updating PLL data when the parent rate changes. yes, that's a whole thing. let's get into it 🫶

---

🌸 NAME 🌸

__wrpll_update_parent_rate — update PLL data when parent rate changes 💅

---

🎀 SYNOPSIS 🎀

int __wrpll_update_parent_rate (struct wrpll_cfg *c , unsigned long
parent_rate );

---

🦋 ARGUMENTS 🦋

• c — ptr to a struct wrpll_cfg record to write PLL data to ✨
• parent_rate — PLL input refclk rate (pre-R-divider) 💫

---

💖 DESCRIPTION 💖

So what this does is pre-compute some data used by the PLL configuration algorithm, and it does that when the PLL's reference clock rate changes. the whole intention here is to avoid computation when the parent rate stays constant — which is expected to be the common case. iykyk, no cap, that's the vibe check. 🔥

like, it's giving "why do the math again if nothing moved?" and honestly? iconic. 👑

---

⭐ RETURN ⭐

Returns 0 upon success, or -ERANGE if the reference clock rate is out of range. 😭

---

💜 SEE ALSO 💜

• Kernel file ./drivers/clk/analogbits/wrpll-cln28hpc.c
• __wrpll_calc_filter_range(9)
• __wrpll_calc_fbdiv(9)
• __wrpll_calc_divq(9)
• wrpll_configure_for_rate(9)
• wrpll_calc_output_rate(9)
• wrpll_calc_max_lock_us(9)

---

fr fr go read those too, bestie, they're the whole squad 🧚

that's the whole page, hope it ate 💅 — this one came from ./drivers/clk/analogbits and the date on it is October 2026, so like, future vibes only 🌈✨ mwah, ily, go configure some PLLs 🎀