RFC 296

DS-1 Display System

๐Ÿ“… published January 1972, from ietf

DS-1 DISPLAY SYSTEM ๐ŸŽ€

RFC 296, by D. Liddle of Owens-Illinois, Inc., NIC 8484, dated January 1972. The header doesn't list a category, and it doesn't say what this obsoletes or updates. ๐Ÿงš

Introduction โœจ

okay so the DS-1 is a proposed modular display system that pairs a 512 x 512 line, 60 line per inch plasma display/memory panel with a mini-processor ๐Ÿ’– the whole point is combining display memory with local processing power, so it can run in three different modes:

  1. As an "intelligent terminal" ๐Ÿ’ป that works on data coming in from the network or a local host, doing things like text editing and picture processing.
  2. As a passive terminal ๐Ÿซถ where the mini-processor takes existing display lists, command strings, and data structures meant for storage tube terminals (or other devices) and converts them into the right format for the plasma display. there's even a software module for simulating the ARDS 100A, which is so thoughtful ๐Ÿฅน
  3. As an offline system ๐ŸŒธ where the processor runs as a stand-alone mini-computer for debugging, editing, and general display work.

the DS-1 is made of a display module, a processor module, and a keyboard (see Figure 1) ๐ŸŽ€ the display model is a DIGIVUE_ display/memory unit, model 512-60, made by Owens-Illinois, Inc., and it holds the plasma panel and its drive circuitry โœจ the processor module was specially designed and built for the DS-1 by the Raytheon Company ๐Ÿ‘‘

there's a modem inside the processor module, which gets covered in later sections ๐Ÿ“ก there's also an RS 232 interface as an alternative, for connecting to a TIP or a teletype-compatible system ๐Ÿ“

[Figure 1 DS-1 Display System*]

besides the display module and the processor, the DS-1 has a data transmission modem, an ASCII keyboard, and an I/0 interface that supports lots of external devices ๐Ÿฆ‹ the mechanical design is all about flexibility, so the keyboard and display module can be oriented independently of the processor module. main character energy ๐Ÿ’…

software comes with the DS-1 too, for things like text editing, vector generation, data management, and various I/0 routines ๐Ÿ’œ

the DS-1 is mostly meant to be an online terminal ๐ŸŒˆ offline mode is for programming and data prep stuff that doesn't need the host computer. so in describing how it runs, offline operations are basically a subset of online ones, where the only I/0 functions are local ๐Ÿงš the I/0 operations use "direct" input/output instructions, which is a special feature of the 700 series machines built at the Raytheon Company โญ a single instruction does the job: DIN for input and DOT for output. DOT makes the addressed external device accept the data currently in the accumulator, and DIN makes it send data to the accumulator, both over the data buss ๐Ÿซถ

the plasma display's X and Y address registers are seen by the processor as output devices, and the modem is the other basic output device ๐ŸŽ€ the keyboard and input modem are the basic input devices, and there's also an optional cassette tape system for loading programs ๐Ÿ’– those devices, plus how other peripherals connect, get covered in later sections โœจ

Figure 2 is a block diagram of the basic DS-1 configurations, focused on the I/0 structure ๐Ÿฆ‹ the processor's main job is restructuring input data into the right output form, either modem-to-display (computer to operator) or keyboard-to-modem (operator to computer) ๐ŸŒธ that processing includes:

[Figure 2 US-1 I/0 Configuration*]

string and stack manipulation ๐Ÿ“ character suppression or translation ๐Ÿ”ฅ vector construction from endpoint data or from character-encoded line drawing commands ๐ŸŒˆ and data stream protocol and management ๐Ÿ‘‘ so the input/output character stream over the modem or channel stays compatible with the host computer, while the keyboard inputs and display outputs get handled effectively and efficiently ๐Ÿ’…

the real big deal about the DS-1 as a new display terminal is its plasma display/memory unit ๐Ÿ˜ญ because it has inherent memory and selective erase capability, it can be addressed asynchronously, it doesn't need any special "refresh" or access to buffer memory, and it's indistinguishable from any other output medium, like tape ๐Ÿงš from the operator's side, it has really good human factors: high contrast, "crisp" line dimensions, no jitter, flicker, or distortion, and the ability to rear-project pictorial or tabular data from slides or microfiche, for example ๐Ÿคฉ

both the display module and the processor get described in detail in later sections, along with the mechanical construction, communication interfaces, keyboard, and system software ๐Ÿซถ

2. Display Module ๐Ÿฆ‹

the DS-1 display module is an Owens-Illinois DIGIVUE_ display/memory unit, Model 512-60 ๐Ÿ’– it contains the plasma panel, the drive electronics, and the display logic, and each of those three assemblies is described in the paragraphs below โœจ

PANEL ๐ŸŒธ

the DIGIVUE_ display panel (aka the plasma panel) is a matrix device ๐ŸŽ€ it's built from two pieces of 1/4" plate glass, with very fine gold electrode lines deposited on them ๐Ÿฅน those electrodes are then completely covered by a dielectric film. the two plates get sealed together with a gap of a few thousandths of an inch between them, and their electrode patterns are oriented orthogonally to each other ๐Ÿ’…

then the "sandwich" is baked out and pumped down to high vacuum, backfilled with a gas mixture that's mostly Neon, and sealed off ๐ŸŒˆ flexible ribbon cable connectors get added, and that finishes the panel ๐Ÿงš the device is fat, roughly _" thick, and virtually transparent ๐Ÿซง

the panel works so that any location (any x, y intersection) can be individually turned "on" or "off" as a source of visible light ๐Ÿ’œ and each location has "memory," staying in its "on" or "off" state until a new selection signal changes it ๐Ÿ˜ญ

an AC voltage is applied between all x and all y electrodes in parallel, so an AC signal below the breakdown potential is always across the gas. this is called the sustaining voltage, VS ๐Ÿ”ฅ to address a single x,y point, a voltage pulse, VP, is applied to the matching x and y lines, so that the total addressing voltage at their intersection is:

V ADD = VS + 2VP,

which goes above the breakdown potential of the gas and starts a discharge โšก

since the electrodes are covered by a dielectric, no discharge current can flow in the external circuit ๐Ÿ™ˆ instead, the ions and electrons from the discharge get carried by the applied field and deposited as stored charge on the dielectric surfaces ๐ŸŒธ this keeps going until the net field is nearly zero, which quenches the discharge after about one microsecond โญ when the AC sustaining voltage flips polarity, that stored charge acts as a bias voltage, adds to the sustaining signal, and makes a new discharge ๐ŸŽ€ that stored charge causes another discharge on the next half cycle, and so on ๐Ÿ’–

so once addressed, a single x,y location keeps discharging twice every sustainer period, which is about 100 thousand times per second ๐ŸŒˆ it looks like a continuous glow to the eye โœจ a sustained location can be turned off by addressing it so the stored charge goes back to zero ๐Ÿ’… so a location, or "cell," can be turned on or off in a bistable, random access manner ๐Ÿฆ‹

the plasma display has a bunch of super useful visual characteristics ๐Ÿซถ its transparency lets rear-projected data from microfilm, color slides, maps, forms, and so on get "mixed" with the dynamic, computer-generated data (characters, plots, graphics, etc.) ๐Ÿ“ on top of the high brightness of the gas discharge, the contrast ration is extremely nigh ๐Ÿ”ฅ the panel in the model 512-60 has 512 x 512 lines at 60 lines per inch ๐Ÿ‘‘ that high resolution and large size means highly readable characters and graphics can be mixed without distortion or jitter ๐Ÿ˜ญ dot matrix characters look especially good, since the "dots" of the discharge sites have very clean, crisp dimensions ๐Ÿ’œ

a big system feature of the plasma display matrix is its random access memory property ๐Ÿงš unlike storage tube displays, it can be selectively erased as well as written, so you can change a single point, curve, or character without altering anything else on the panel ๐ŸŒˆ large quantities of text, time histories of measured data, or complex memory. this allows more efficient use of the processor and simpler data management within computer memory ๐Ÿ’–

the 512-60 panel used in the DS-1 will have an active area of 8.5 x 8.5 inches, with 512 x 512 lines ๐ŸŽ€ there's also an extra 4 line peripheral border around the addressable area, for conditioning the discharge sites โœจ

the back of the panel will be frosted with an optically diffusing surface, suitable for projecting optical images ๐Ÿฆ‹ a circularly-polarizing neutral density filter with anti-glare coating will go on the front of the display ๐Ÿซถ the brightness and contrast will be good enough for a normal lighted laboratory area ๐ŸŒธ

Drive Electronics โšก

the drive electronics for the display module are the standard Owens-Illinois circuits required to run a 512 x 512 line panel as part of the model 512-60 standard display unit ๐Ÿ’… they include a sustaining generator, which keeps cells in their appropriate state ("on" or "off") after the addressing signal is removed ๐ŸŒˆ they also have pulse-forming circuits that generate and properly mix addressing pulses at the selected panel sites ๐Ÿงš

the sustainer runs with a basic period of 20 microseconds, with a peak voltage of about 130 volts ๐Ÿ’œ the exact voltage levels, frequency, and waveshape get adjusted for optimal performance, subject to power supply constraints and data rate requirements ๐Ÿ“

the address circuits are multiplexed to cut down on the number of active circuits needed, and they use a non-linear mixing scheme for line selection ๐Ÿ”ฅ a pulse of 100 volts is applied with the right time phase to write and erase ๐Ÿ’– the pulse is disabled on all lines except the selected line pair ๐Ÿ‘‘

bulk erasure is also provided, where the entire panel gets erased in two sustainer periods ๐ŸŒˆ a high density power supply provides the sustaining, addressing, and logic level voltages ๐Ÿ˜ญ the design uses high-frequency invertors and switching regulation for max efficiency and smaller size ๐Ÿซถ it needs about 250 watts and will live inside the processor module โœจ

Display Logic ๐Ÿ’…

The display module's logic is basically the timing boss ๐Ÿ’… It runs the timing and control for the sustaining generator and the address pulses, and it's also the translator between itself and the processor module at logic level. Everything is TTL compatible ๐Ÿ”Œ It has 2 nine-bit address ports, X0-X8 and Y0-Y8, which [not legible*], using absolute binary code, to pinpoint the x,y intersection you want to address ๐ŸŽฏ Those addresses only get accepted when you send a write command on W or an erase command on E ๐Ÿซถ Everything has to stay rock steady until the display says it's done accepting the data and finishing the operation, and it tells you that on the status line, which is a logic level output from the display unit. There's also an extra control line, B, that works together with the H line to bulk erase the whole screen in one go ๐Ÿงนโœจ

The model 512-60 display unit proposed in this document is a serial address type, so it writes or erases one point every 20 u/seconds ๐Ÿฆ‹ That's still fast enough to draw vectors at more than 800 inches/second ๐Ÿ”ฅ Characters in a 5x7 dot matrix can be written at about 1400 characters per second ๐Ÿ’–

A parallel address type display unit is being developed at Owens-Illinois right now ๐Ÿ‘€ Once it's available, it'll be compatible with the DS-1 system with no modification to the processor required ๐ŸŽ€ It addresses 16 lines in parallel, so it can display more than 6,000 characters per second, or generate a complete page in .330 seconds ๐Ÿ˜ญ๐Ÿ™Œ


3. Processor Module โœจ

The processor is a minicomputer (Figure 1) that takes in ASCII encoded commands and generates outputs to control how the display module writes information ๐Ÿง  It's the one storing information, data, and instructions, and it keeps the flow of information moving between the terminal's Keyboard, Modems, Display Module, and Program Loading Device (Figure 2) ๐Ÿ’œ

In a typical operation, the processor pulls in input commands from the modem and the keyboard, then sends instructions to the display module driver circuitry to produce the required characters, vectors, or editing programs ๐ŸŒธ

Instructions and data are stored in 16 bit words ๐Ÿ“ Arithmetic functions are performed in 2's complement form. The basic machine cycle time is 1.6 microseconds โฑ๏ธ

The major functional units of the processor are (Figures 3 & 4):

  • Memory
  • Memory Address Register
  • Program Counter
  • Instruction Register
  • Accumulator
  • Instruction Processing Synchronizer
  • Terminal I/O Circuitry

Here's a quick rundown of each one ๐Ÿ‘‘

Memory

There's an operational memory of 2048 - 16 bit words plus bootstrap memory of 64-16 bit words ๐Ÿงš The 2038 word memory is a Random Address Memory (RAM), and it stores the character generator, the vector generator, and the editing programs needed for the terminal's specific operational requirements ๐Ÿ’… Using RAM gives you flexibility:

[Figure 3 Processor Data Flow*]

[Figure 4 Instruction Processor Synchronizer*]

to alter instruction routines and tailor the terminal for the application ๐ŸŽจ Since the terminal uses RAM, an operational program loading device (a magnetic tape cassette read/write recorder) is proposed, so the operational program can be loaded when the terminal is turned on ๐Ÿ“ผโœจ

The RAM size is enough to store 128 characters, a vector generation routine, and an instruction set ๐Ÿ’–

The bootstrap memory stores a terminal start up program that gets the terminal ready to read instruction data into its operational memory from external sources ๐Ÿซถ Read Only Memory (ROM) devices are used for the bootstrap memory. Both the RAM and the ROM memories are made up entirely of MOS ๐Ÿ”ฅ

Memory Address Register

The Memory Address Register (MA) is a twelve bit register that can be loaded with the program counter or the address portion of the memory data ๐Ÿฆ‹

Program Counter

The Program Counter (PC) is a 12 bit counter-register that can be loaded with the address portion of the instruction register ๐ŸŒˆ

Instruction Register

The Instruction Register (IR) is a 16 bit register. 4 bits hold the instruction and 12 bits hold the data associated with that instruction ๐Ÿ’œ It can be loaded with a 16 bit memory word โœจ

Accumulator (AC)

The Accumulator (AC) is a 16 bit shift register that can be loaded with the contents of the program counter, the data inputs, or the arithmetic unit ๐Ÿ”ฅ It's the main character here, honestly ๐Ÿ‘‘

Instruction Processing Synchronizer (IPS)

The Instruction Processing Synchronizer controls the timing and data flow in the processor โฐ It's clocked by its own oscillator, and it calls up instructions from memory, which then dictates the sequence to be followed ๐Ÿงš

Terminal I/O Circuitry

The processor talks to the other parts of the terminal either directly on the I/O bus or through one of three device controllers ๐Ÿ”Œ The controllers are required to make the I/O devices compatible with the processor. Separate controllers are provided for Keyboard, Display Module, and Serial I/O devices ๐ŸŽ€

The I/O Bus includes:

  • 16 Parallel Input Data Lines
  • 16 Parallel Output Data Lines
  • 4 lines for selecting the I/O device to communicate with the processor
  • 4 Lines for specifying the function to be performed
  • 16 sense lines for monitoring the status of each I/O device
  • 2 strobe lines to initiate the transfer of data to and from the I/O devices
  • 1 system clock line

Each of these lines is available at the I/O Bus Connector ๐Ÿงƒ The lines each controller needs depend on the function that controller performs (Figure 4). There are three ports on the Serial I/O Channel Controller: two asynchronous and one synchronous ๐Ÿ’ซ The synchronous one is for an optional cassette tape recorder that can come with the terminal or be bought later ๐Ÿ“ผ The two asynchronous ports are for a teletypewriter modem (not supplied) and a telephone modem that comes with the terminal ๐Ÿ“ž Direct connection with a data processing machine can be done at the I/O bus connector ๐Ÿ’ป

The processor has a single level interrupt that makes it jump to a designated sub-program while automatically storing the contents of all appropriate registers and the return linkage ๐ŸŒธ The mask and unmask instructions gate the interrupt line according to the state of an inhibit flip-flop ๐Ÿ™ˆ The last instruction, Interrupt Return, restores the program counter, accumulator, and overflow indicator to the condition they were in at the time of interrupting โญ

Software

The desired terminal operations, meaning the logical capabilities of the display terminal, are implemented in software ๐Ÿ’… This approach gives a degree of flexibility and versatility to the terminal's editing and display writing. In the display writing area, characters, symbols, and graphics are limited in variety only by the resolution (60 dots per inch) and the size (8-1/2" x 8-1/2") of the display screen ๐Ÿ–ผ๏ธ The flexibility gets an extra boost from memory expandability to 4K (32K optional) ๐Ÿš€

The software is split into two segments: (1) servicing routines for the input modem, the output modem, the keyboard, and the display module, and (2) specific function routines for line generation, editing, point generation, and character generation ๐Ÿงฉ

Typical software processing starts with the program in an idle loop, checking the input sense line ๐Ÿ‘€ When a bit is ready in the modem, the sense line goes true, the processor skips, and the program inputs the bit. The sense line resets. The program counts the bit, saves it, and goes back to the idle loop to wait for the next bits ๐Ÿ” As each bit comes in, it's stored in proper sequence. When a word is entirely memory, it's moved to another memory location where it can be decoded ๐Ÿ“ฆ The program resets the input, counts for the next word, and transfers to the task routine, which analyzes the command and figures out which segment of the program handles the function ๐ŸŽฏ

Let's say the program was told to plot a character ๐Ÿ’– The program computes a table from the value of the character code. The table holds a compacted image of the dots representing the character. The image gets unpacked from the table into a temporary hold area. Then, starting at the top left corner, the program outputs the coordinates and the one or zero value of the image ๐ŸŒˆ The next point is output in the next lower Y position. This repeats until 14 bits have been output (one column) ๐Ÿงฎ The program resets the Y coordinate to the original Y and increments the X. The next column is output the same way as the first ๐Ÿซถ

When nine columns have been output, the program goes back to the idle loop ๐ŸŽ‰

Instruction Description

Instructions and data are in the form of 16 bit words. Arithmetic functions are performed in 2's complement form. The following word formats apply ๐Ÿงพ

Instruction              0  1  3  4     15
                         I   OP    Address

Address Data             0  1           15
                         I     Address

Data                     0 1            15
                         S      Data

The instruction format gives 1 bit for indirect addressing, 3 bits for the operations code (OOP), and 12 bits for the address ๐Ÿ’œ The address data format has 15 bits of address and 1 bit for indicating indirect addressing. The data word format includes 1 sign bit and 15 bits for data โœจ

Logical control of data flow in the display processor is centered around the accumulator ๐Ÿ‘‘ Most operations involve it, or involve sensing data conditions in it. The 19 processor operations represent 6 types of instructions:

  • Data Movement (Through the accumulator)
  • Logical operations (on accumulator contents)
  • Condition Checking
  • Input/Output
  • Jump Control
  • Indexing

Each of these instruction types gets a quick explanation next. Check out Appendix I for the complete instruction set ๐Ÿ“–๐ŸŒŸ

Data Movement Instructions - CLA, LDA, ADD, STC

These four instructions enable the accumulator to be cleared or loaded with data ๐Ÿงน They also add a word to the accumulator's contents, and they let the accumulator contents be stored in memory ๐Ÿ’พ

Logical Operations - AND, CMP, RAL, SAL

These four instructions let a word in memory be logically "anded" to the accumulator ๐Ÿค They form the 2's complement of the accumulator's contents, enable a left rotation of the accumulator contents, and permit a left shift of the accumulator's contents ๐Ÿ”„

Condition Checking - SAZ, SNZ, SAC, SNA, SNO

These five instructions allow for various condition checks ๐Ÿ” SAZ and SNZ check the accumulator for zero or non-zero contents. SAG and SNA check any bit position in the accumulator for a 1 or 0 setting. SNO checks for accumulator overflow ๐Ÿ™Œ

Input/Output - SS, DIN, DOT

The SS instruction is basically the "are you ready?" check for devices hooked up to the processor, like the modem or display module ๐Ÿ’– Actual data moves through the accumulator, one word at a time. DIN pulls one 16-bit word from an external device into the accumulator, and DOT sends one 16-bit word from the accumulator out to an external device ๐Ÿซถ Which device gets targeted is set by the device address field of the instruction, and these instructions are how the controller talks to a whole bunch of peripheral units โœจ

Jump Control - JMP, JSR

okay so these are the instructions that let the program change where it's going ๐Ÿฆ‹ JMP is an unconditional jump, meaning control goes straight to a designated memory location, no questions asked ๐Ÿ’… JSR gives the program subroutine powers. Running a JSR means saving the return address to the jump at a designated location ๐Ÿงš And here's the iconic part: if you designate the spot for the return address as not being in line with the code that's running, the program in execution can live in read only memory ๐Ÿ’œ

Indexing - IAS

these instructions give the order code an indexing facility ๐ŸŒธ The indexing happens in the memory location named in the address field of the IAS instruction, and because of that, multiple indexing is possible ๐Ÿ‘‘

All of the above instruction types add up to a fundamental but general programming capability ๐Ÿ’– On top of that, a basic symbolic assembly language was built, and people use it to write programs which do character, assembler program; the assembler is written in FORTRAN language โœจ

Modem

The display terminal comes with a modem so the I/O controller can talk to a telephone line ๐Ÿ“ž It works asynchronously through one of the three I/O controller ports (Figure 5) ๐ŸŒˆ It's an FSK unit, running at data rates from 0 to 1800 bps in four wire full-duplex mode, and from 0 to 1200 bps in half-duplex mode ๐Ÿ’… In four wire full-duplex, the local and remote modems each operate completely independently, so either one can start a data transfer sequence at any time by activating the Request To Send signal ๐Ÿ”ฅ The sequence wraps up when the RTS signal is dropped at the originating modem ๐Ÿฆ‹

In half-duplex mode, the modem can handle any data format ๐Ÿ’œ Which modem is transmitting and which is receiving is decided by the status of the Request To Send signal coming from the processor ๐ŸŽ€

The modem can also go over a dial-up network in half-duplex mode ๐Ÿ“ž To do that, you need the November, 1968, Data Access Arrangement, number F-57951, supplied by the Bell System ๐ŸŒธ In this setup, the call gets started from the phone set tied to the Data Access Arrangement ๐Ÿงš On the remote end, someone manually answers, and the data key on the phone set gets put in the data position โญ

Keyboard

A multimode keyboard with standard ASCII character-to-key assignments is proposed ๐ŸŽ€ It covers upper and lower case alphanumerics, special function keys, and codes for editing operations ๐Ÿ’–

[Figure 5 DS-1 I/O Data Lines*]

Section 4 Mechanical Considerations โœจ

The DS-1 is made of three separate self-contained sub-units: the display module, the processor module, and the keyboard ๐ŸŒˆ

Display Module

The Display Module holds the plasma panel and the driver electronics ๐Ÿ’œ Its overall size is 14" W x 14" H x 61/2" D, and it weighs approximately 25 pounds ๐Ÿฆ‹ You get an 8-1/2" x 8-1/2" viewing area ๐Ÿ‘‘

Interconnections to this unit are provided at the rear of the assembly ๐Ÿซถ

Processor Module

The processor enclosure holds circuit board assemblies, three separate power supplies, and a cassette tape recorder (optional) ๐Ÿ”ฅ The overall size is approximately 20" W x 6-1/2" H x 26" D, and it weighs approximately 60 pounds ๐Ÿ’…

Input/Output connectors sit at the rear of the enclosure so it can connect to the units it has to interface with ๐Ÿงš

Keyboard

This unit gives you a full alphanumeric keyboard in a desk top enclosure of approximately 15" W x 3" H x 7" D ๐Ÿ“ It includes:

  • The entire displayable character set in the standard ASCII layout.
  • Special Function keys for editing and I/O control.

The touch is similar to an electric typewriter, so it's suitable even for an inexperienced operator ๐ŸŽ€โœจ

Appendix I

DS-1 Instruction Set

The following instructions are provided; ๐Ÿ’–

The execution time for instructions with indirect addressing (optional with instruction marked*) takes one cycle for each indirect level ๐Ÿซถ

   LDA, A, I Load Word      0  1  2  3  4      15
                            I  0  0  0      A

This instruction loads the contents of address A into the accumulator ๐ŸŒธ The previous contents are lost ๐Ÿ’€ The program counter is indexed by 1 ๐Ÿฆ‹

                              Time = 1 cycle*
                            0  1  2  3  4      15
   JMP, A, I, Jump          I  0  0  1      A

This instruction causes program control to be transferred to the address A ๐Ÿงš The contents of the accumulator are not altered โœจ

                              Time = 1 cycle*
                            0  1  2  3  4      15
   JSR, A, I, Jump & Save   I  0  1  1      A
                   Return

This instruction stores the present address plus 1 at the location specified by the contents of memory location A, and transfers program control to location A+1 ๐Ÿ’œ The accumulator is cleared ๐Ÿซง

                              Time = 3 cycles*
                            0  1  2  3  4      15
   ADD, A, I, Add           I  0  1  0      A

This instruction adds the contents of memory at location A to the accumulator ๐Ÿ”ฅ The overflow indicator is set to the appropriate state, and it stays set until the next ADD, IAS, or CLA instruction is processed ๐Ÿ‘‘

                              Time = 2 cycles*
                            0  1  2  3  4      15
   AND, A, I And            I  1  0  0      A

The instruction ands logically the contents of the accumulator with the data stored in Location A ๐Ÿ’… The results is stored in the accumulator ๐ŸŒˆ

                              Time = 2 cycles*
                            0  1  2  3  4      15
   STA, A, I Store          I  1  0  1      A
           Accumulator

This instruction stores the contents of the accumulator in memory Location A ๐ŸŽ€

                              Time = 2 cycles*
   IAS, A, I Index & Skip   0  1  2  3  4      15
             If Zero        I  1  1  0      A

This instruction reads the contents of memory location A and adds 1 to it ๐Ÿ’– The results are then stored back in location A of the memory ๐ŸŒธ If the results of the addition is zero (i.e., an overflow generated), the next instruction is skipped ๐Ÿ˜ญ Otherwise, the next instruction is executed ๐Ÿฆ‹ The accumulator contains the contents of A plus 1 โœจ

                              Time = 3 cycles*
                            0  1  2  3  4  5  6  7  8   11  12  15
   SAL, N Shift             0  1  1  1  0  0  0  0    n
   Accumulator Left

This instruction shifts the contents of the accumulator left by n bits, and the least significant bits become zero ๐Ÿงš

                              Time = 1 cycle*
                            0  1  2  3  4  5  6  7  8   11  12  15
   RAL, N Rotate            1  1  1  1  0  0  0  0    n
   Accumulator Left

This instruction rotates the contents of the accumulator left by n bits ๐ŸŒˆ The most significant bit becomes the initial least significant bit ๐Ÿ’œ

                              Time = cycle*
                            0  1  2  3  4  5  6  7  8    15
   HLT, Halt                0  1  1  1  1  0  0  1

This instruction causes program execution to stop ๐Ÿ™ˆ It's used primarily for debugging purposes. Pressing the RUN button or the SINGLE CYCLE button causes continued execution, either continuous or one cycle respectively ๐Ÿ”ฅ

                              Time = 1 cycle*
                            0  1  2  3  4  5  6  7  8    15
   SAZ Skip Accumulator     0  1  1  1  0  1  0  0
   Zero

This instruction causes the next instruction to be skipped if the accumulator is zero ๐Ÿ‘‘

                              Time = 1 cycle*
                            0  1  2  3  4  5  6  7  8    15
   SNZ Skip Accumulator     1  1  1  1  0  1  0  0
   Non-Zero

This instruction causes the next instruction to be skipped if the accumulator is non-zero ๐Ÿ’…

                              Time = 1 cycle*
                            0  1  2  3  4  5  6  7  8  11  12  15
   SAC, B Skip              1  1  1  1  0  1  0  1    B
   Accumulator

This instruction causes the next instruction to be skipped if bit number B is one (1) ๐ŸŽ€ The most significant bit is zero, and the least significant is 15 ๐Ÿฆ‹

                              Time = 1 cycle*
                            0  1  2  3  4  5  6  7  8    15
   SNO Skip No                 1  1  1  0  0  0  0
   Overflow

This instruction causes the skipping of the next instruction if the overflow is not set ๐ŸŒธ

                              Time = 1 cycle*
                            0  1  2  3  4  5  6  7  8    15
   CMP Complement              1  1  1  0  0  1  1
   Accumulator

This instruction stores the 2's complement of the accumulator in the accumulator ๐Ÿงš

                              Time = 1 cycle*
                            0  1  2  3  4  5  6  7  8  11  12  15
   DOT Data Output             1  1  1  0  0  0  1   Add    Func.

This instruction causes the contents of the accumulator to be gated to the DIO Data buss, and a Data Output Strobe (DOS) pulse to be transmitted to the peripheral device ๐Ÿ’– The device uses that pulse to store the contents of the Standard I/O Buss ๐Ÿซถ The device Address and Function data is transmitted simultaneously with the data โœจ

                              Time = 1 cycle*
                            0  1  2  3  4  5  6  7  8  11  12  15
   DIN Data Input              1  1  1  1  1  0  0   Add    Func.

This instruction causes the device address and function data to be transmitted as in the DOT instruction ๐ŸŒˆ When the device detects this address, function, and DATA Input Strobe (DIS), it gates its data onto the Standard I/O Buss ๐Ÿฆ‹ Deactivating the Data Input Strobe indicates that the data has been received and stored ๐Ÿ’œ

                    0  1  2  3  4  5  6  7  8  9  10  11  13  14  15
   INR Interrupt    0  1  1  1  1  1  1  1  0  0   0     L    0    0
   Return

This instruction restores the Program Counter, the Accumulator, and the Overflow indicator to the conditions they had prior to servicing the present active level ๐Ÿ‘‘ Parameter L must be set to the level being processed for correct return linkage ๐Ÿ”ฅ The interrupt returns to the idle state ๐ŸŽ€ See pages 3-3 and 3-4 โœจ

                              Time = 4 cycles*
                            0  1  2  3  4  5  6  7  8    15
   MSK Mask Interrupts      1  1  1  1  1  1  1  0

This instruction inhibits the interrupt system from causing any interrupt to be processed ๐Ÿ™ˆ Interrupts that are waiting or received while interrupts are _masked_ will be processed when they are unmasked ๐Ÿ’… See pages 3-3 and 3-4 ๐ŸŒธ

                              Time = 1 cycle*
                            0  1  2  3  4  5  6  7  8    15
   UNM Unmask Interrupts    0  1  1  1  1  1  1  0

This instruction causes the interrupt system to be processed in the normal manner ๐Ÿงš See pages 3-3 and 3-4 ๐Ÿ’–

okay so this part is super short, bestie ๐Ÿ˜ญ but we still gotta be precise ๐Ÿ’…

                            Time = 1 cycle*
the original is missing its figures and some text, so there's nothing more here to rewrite ๐Ÿซถ
* Please see the PDF file for figures and missing text (not legible in
  the original).

that's the whole part 4, periodt โœจ๐ŸŽ€

๐Ÿ“ฆ where this page comes from