sg2042_get_pll_ctl_setting(9)

💖 NAME 💖

okay so bestie, this is the sg2042_get_pll_ctl_setting(9) page from the Kernel API Manual, and it's literally the function that — based on the given FOUTPISTDIV and the input FREF — calculates the REFDIV/FBDIV/PSTDIV1/POSTDIV2 combination for the pllctrl register. no cap, that's the whole vibe ✨

🌸 SYNOPSIS 🌸

int sg2042_get_pll_ctl_setting (struct sg2042_pll_ctrl *best , unsigned
long req_rate , unsigned long parent_rate );

🎀 ARGUMENTS 🎀

• best — output to hold calculated combination of REFDIV/FBDIV/PSTDIV1/POSTDIV2. it's the lil container for the winning combo 💅
• req_rate — expected output clock rate, i.e. FOUTPISTDIV. bestie, this is the rate you're manifesting ✨
• parent_rate — input parent clock rate, i.e. FREF. the source energy ⭐

🔥 RETURN 🔥

• 0 — OK ✅
• -EINVAL — invalid argument 😭

so if you get 0, slay; if you get -EINVAL, check ur args, bestie 🫶

🦋 SEE ALSO 🦋

the kernel file is ./drivers/clk/sophgo/clk-sg2042-pll.c, and the related besties are:

• struct sg2042_pll_clock(9)
• sg2042_pll_recalc_rate(9)
• sg2042_pll_get_postdiv_1_2(9)
• sg2042_clk_pll_recalc_rate(9)

k bye bestie 🫶 this page's source/version line says ./drivers/clk/sophgo, the date is October 2026, and the title is sg2042_get_pll_ctl_setting(9). mwah 💋