sg2042_clk_pll_recalc_rate(9)

💅 sg2042_clk_pll_recalc_rate(9) — from the Kernel API Manual, bestie 🎀

okay so picture this: it's a kernel API manual page, it's about clocks, and it's literally the recalc_rate callback for pll clks. buckle up ✨

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💖 NAME 💖

sg2042_clk_pll_recalc_rate — the recalc_rate callback for pll clks. that's it, that's the whole vibe 🫶

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🌸 SYNOPSIS 🌸

unsigned long sg2042_clk_pll_recalc_rate (struct clk_hw *hw , unsigned
long parent_rate );

like yes, it returns an unsigned long, and yes, it takes two things. we'll get to those 🧚

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🦋 ARGUMENTS 🦋

• hw — this is the ccf hook situation, used to get at sg2042_pll_clock. ccf uses it to hook, iykyk 💫
• parent_rate — the parent rate. that's the parent's rate. no notes 💅

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✨ DESCRIPTION ✨

so the way this works: this function gets called through clk_get_rate, and it returns the current rate — after decoding the reg value. decoding!! the reg value!! it's giving detective energy 🔍👑

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🔥 RETURN 🔥

the current rate, all recalculated and fresh. slay 💖

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👑 SEE ALSO 👑

• the kernel file ./drivers/clk/sophgo/clk-sg2042-pll.c — go read it, it's iconic
• struct sg2042_pll_clock(9)
• sg2042_pll_recalc_rate(9)
• sg2042_pll_get_postdiv_1_2(9)
• sg2042_get_pll_ctl_setting(9)

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and that's the page, bestie 💜 it lives over at ./drivers/clk/sophgo, stamped October 2026, and it's filed under sg2042_clk_pll_recalc_rate(9) — mwah, go forth and read your clocks 🌈⭐🍓