r600_cs_common_vline_parse(9)

πŸ“¦ version 7.3.1, in nixpkgs unstable

🌸 NAME

okay so r600_cs_common_vline_parse is the common vline parser πŸ’… β€” and yeah, that's literally the name section. this little page lives in the Kernel API Manual, and it's about one very specific kernel helper. bestie, we're going in. 🫢

✨ SYNOPSIS

int r600_cs_common_vline_parse (struct radeon_cs_parser *p , uint32_t
*vline_start_end , uint32_t *vline_status );

πŸŽ€ ARGUMENTS

  • p β€” parser structure holding parsing context. it's giving "i hold the context" main character energy.
  • vline_start_end β€” table of vline_start_end registers. the registers are right there, bestie.
  • vline_status β€” table of vline_status registers. status table, slay.

πŸ’… DESCRIPTION

okay so userspace sends a special sequence for VLINE waits. the whole lil choreo is:

  • PACKET0 - VLINE_START_END + value
  • PACKET3 - WAIT_REG_MEM poll vline status reg
  • RELOC (P3) - crtc_id in reloc.

this function parses this and relocates the VLINE START END and WAIT_REG_MEM packets to the correct crtc. it also detects a switched off crtc and nulls out the wait in that case β€” yes, that's the dramatic part πŸ’€. this function is common for all ASICs that are R600 and newer. the parsing algorithm is the same, and only differs in which registers are used.

the caller is the ASIC-specific function which passes the parser context and ASIC-specific register table 🫢.

πŸ”₯ SEE ALSO


k bye bestie πŸ’– this page is from the Kernel API Manual, sourced from ./drivers/gpu/drm/radeon, dated October 2026, and the star is r600_cs_common_vline_parse(9) βœ¨πŸ¦‹

πŸ“¦ where this page comes from