igc_write_ivar(9)

πŸ“¦ version 7.3.1, in nixpkgs unstable

πŸŽ€ NAME πŸŽ€

Hey bestie πŸ’– welcome to igc_write_ivar(9), straight outta the Kernel API Manual. This page is all about igc_write_ivar β€” configure ivar for given MSI-X vector. That's the name, that's the vibe, periodt.

✨ SYNOPSIS ✨

No cap, here's the exact signature:

void igc_write_ivar (struct igc_hw *hw , int msix_vector , int index , int offset );

🌸 ARGUMENTS 🌸

Okay so this function takes four things, and every single one matters:

  • hw β€” pointer to the HW structure. Your hardware main character 🫢
  • msix_vector β€” vector number we are allocating to a given ring.
  • index β€” row index of IVAR register to write within IVAR table.
  • offset β€” column offset of in IVAR, should be multiple of 8. Lowkey important: multiple of 8, bestie.

πŸ¦‹ DESCRIPTION πŸ¦‹

The IVAR table consists of 2 columns, each containing a cause allocation for an Rx and Tx ring, and a variable number of rows depending on the number of queues supported. So it's giving tiny-grid energy: two columns, cause allocation for Rx and Tx rings, and the row count is not fixed β€” it changes with how many queues are supported. Slay πŸ’…

πŸ’– SEE ALSO πŸ’–

Go be nosy, bestie β€” these are all the neighbors πŸ‘‘:


Source / version / date sign-off: ./drivers/net/ethernet/intel/igc Β· October 2026 Β· igc_write_ivar(9) β€” mwah, bye bestie πŸ’‹βœ¨

πŸ“¦ where this page comes from