igc_setup_mrqc(9)

πŸ“¦ version 7.3.1, in nixpkgs unstable

✨ igc_setup_mrqc β€” the igc_setup_mrqc(9) glow-up πŸ’…

okay so we're in the Kernel API Manual today bestie, and the star of the show is igc_setup_mrqc(9) β€” the little function that handles the multiple receive queue control registers. yes it's a mouthful, no we're not changing the name, it's iconic as is πŸŽ€


🌸 NAME 🌸

igc_setup_mrqc β€” configure the multiple receive queue control registers

like, it literally sets up the MRQC registers. that's the whole vibe. no cap.


πŸ¦‹ SYNOPSIS πŸ¦‹

void igc_setup_mrqc (struct igc_adapter *adapter );

returns void, takes one pointer, does its little register dance and dips. main character energy fr fr ✨


πŸŽ€ ARGUMENTS πŸŽ€

  • adapter β€” the Board private structure. that's it. that's the one (1) argument. she's low maintenance, we love that for her 🫢

πŸ’– SEE ALSO πŸ’–

okay this is the part where the page absolutely SPILLS the tea β€” there are SO many cross-references and honestly every single one of them ate. grab a snack, here we go:

the source file itself, obviously:

  • the kernel file ./drivers/net/ethernet/intel/igc/igc_main.c β€” go read it, it's giving lore πŸ‘‘

link + hw control besties:

tx ring cleanup crew (they keep it tidy):

rx ring cleanup crew (equally tidy, equally beloved):

configure era (rings and control registers):

mac filter + multicast address stuff:

rx processing pipeline (where the packets get their moment):

filter management, both adding and deleting, because balance:

interrupts, vectors and itr β€” the whole msix cinematic universe:

lifecycle, stats, open/close, error handling β€” the full character arc:

bestie that's the entire friend group. every single one linked, none skipped, that's the rule πŸ’€

and that's the page! no warnings, no bugs section, no environment variables β€” she's short and sweet and we respect her for it 🌈

sign-off time πŸ’œ: this little beauty lives in the source tree at ./drivers/net/ethernet/intel/igc, and it's stamped October 2026. go forth, configure those multiple receive queue control registers, and slay πŸŽ€βœ¨πŸ‘‘

πŸ“¦ where this page comes from