i10nm_get_imc_num(9)

💖 i10nm_get_imc_num(9) 💖

okay bestie, welcome to the Kernel API Manual ✨ — this one's a little function from the kernel's EDAC corner and honestly? she's doing more than she looks like she's doing. let's get into it 🫶

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🌸 NAME 🌸

i10nm_get_imc_num — get the number of present DDR memory controllers 💅

✨ SYNOPSIS ✨

int i10nm_get_imc_num (struct res_config *cfg );

🎀 ARGUMENTS 🎀

• cfg — the pointer to the structure of EDAC resource configurations. that's it, that's the whole argument list, she travels light 🦋

👑 DESCRIPTION 👑

ok so here's the tea, and it genuinely depends on which CPU you're running ☕

• For Granite Rapids CPUs: the number of present DDR memory controllers is read at runtime, and that runtime value overwrites the value statically configured in cfg->ddr_imc_num. so like, the static number gets gently pushed aside and the live one takes main character energy 🔥
• For other CPUs: the number of present DDR memory controllers is just the statically configured value in cfg->ddr_imc_num. no runtime reading, no drama, it is what it is 💀

so basically: Granite Rapids gets the fresh dynamic count, everyone else keeps the one that was already written into the config. periodt 🌈

⭐ RETURN ⭐

• 0 on success 🎉
• < 0 on failure 😭

ngl, that's the entire return contract — no secret bonus values, no in-between, just success or a negative number telling you it went sideways.

🦋 SEE ALSO 🦋

• Kernel file ./drivers/edac/i10nm_base.c
• get_gnr_mdev(9)
• get_ddr_munit(9)
• i10nm_imc_absent(9)

go read those too, they're the rest of the friend group 💜

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and that's the whole page!! sign-off time: this cutie lives in ./drivers/edac, hails from October 2026, and answers to i10nm_get_imc_num(9) — mwah 💋🧚