drm_dp_tunne...ng_supported(9)
π drm_dp_tunnel_128b132b_lane0_mapping_supported(9) π
okay bestie, welcome to the Kernel API Manual β yes that's the manual name, we're in kernel land now, put your hair up π
This one's a little yes/no check about whether lane 0 is mapped the way the DPRX expects on a tunneled 128b/132b link. Very niche, very iconic, let's get into it β¨
πΈ NAME πΈ
drm_dp_tunnel_128b132b_lane0_mapping_supported β literally just checks if 128b/132b lane 0 mapping is supported. that's the whole vibe π
β¨ SYNOPSIS β¨
bool drm_dp_tunnel_128b132b_lane0_mapping_supported (const struct
drm_dp_tunnel *tunnel );
she takes one arg and hands you back a bool. simple. clean. main character energy π
π¦ ARGUMENTS π¦
tunnelβ the tunnel object. yes, that's it, that's the whole argument list. go off π
π DESCRIPTION π
so here's the tea π β this function checks whether the DP-out adapter always maps lane 0 the way the DPRX expects it on a tunneled 128b/132b link.
- if it returns
true, then one- and two-lane configurations with UHBR link rates can always be used. slay, no notes πβ¨ - if it returns
false, using one or two lanes with UHBR link rates may cause a lane-count conversion failure in the DPRX π and that means the source has to take corrective action during link training. not the vibe but okay.
if you want the receipts, see DP Standard v2.1b, section 3.5.2.16.3, 128b/132b DPRX Lane Count Conversion Failure Indication and Corrective Action. iykyk π
meanwhile β a four-lane configuration can always be used, as long as the DPRX supports it, no matter what this function returns. so four lanes is the unbothered queen of the situation π
and yes, she returns true if the DP-out adapter supports the 128b/132b lane 0 mapping. that's the return value, bestie, that's it π«Ά
π SEE ALSO π
the source file, living its best life at:
Kernel file ./drivers/gpu/drm/display/drm_dp_tunnel.c
and the whole friend group of related functions, all of them, no gatekeeping π
drm_dp_tunnel_get(9)drm_dp_tunnel_put(9)drm_dp_tunnel_set_io_error(9)drm_dp_tunnel_detect(9)drm_dp_tunnel_destroy(9)drm_dp_tunnel_enable_bw_alloc(9)drm_dp_tunnel_disable_bw_alloc(9)drm_dp_tunnel_bw_alloc_is_enabled(9)drm_dp_tunnel_pr_optimization_supported(9)drm_dp_tunnel_alloc_bw(9)drm_dp_tunnel_get_allocated_bw(9)drm_dp_tunnel_update_state(9)drm_dp_tunnel_128b132b_supported(9)drm_dp_tunnel_128b132b_dprx_rates(9)drm_dp_tunnel_max_dprx_rate(9)drm_dp_tunnel_max_dprx_lane_count(9)drm_dp_tunnel_available_bw(9)drm_dp_tunnel_atomic_get_state(9)drm_dp_tunnel_atomic_get_old_state(9)drm_dp_tunnel_atomic_get_new_state(9)drm_dp_tunnel_atomic_set_stream_bw(9)drm_dp_tunnel_atomic_get_required_bw(9)drm_dp_tunnel_atomic_get_group_streams_in_state(9)drm_dp_tunnel_atomic_check_stream_bws(9)drm_dp_tunnel_mgr_create(9)drm_dp_tunnel_mgr_destroy(9)
π sign-off π
source of the whole situation: ./drivers/gpu/drm/display β dated October 2026, same title energy as the top, drm_dp_tunne...ng_supported(9) π«
mwah, go ship that UHBR link, bestie π πΈπ¦
π¦ where this page comes from
- nixpkgs unstable: linux-manual 7.3.1
- π girlified by deepseek-ai/DeepSeek-V4.1-Flash-1017 on : a language model's rewrite of the original, under its terms