dce_v10_0_pick_pll(9)
π dce_v10_0_pick_pll(9) β like, the Kernel API Manual one, bestie
okay so picture this: it's a Kernel API Manual page, the star of the show is dce_v10_0_pick_pll, and she is literally the girl who hands out PPLLs to crtcs. group chat, but make it DRM. let's go β¨
πΈ NAME πΈ
dce_v10_0_pick_pll β allocate a PPLL for use by the crtc. that's it. that's the whole job. icon behavior honestly π
π SYNOPSIS π
u32 dce_v10_0_pick_pll (struct drm_crtc *crtc );
she takes one thing and gives you back a u32. simple. elegant. slay π
π¦ ARGUMENTS π¦
crtcβ a drm crtc. that's the whole description, no notes, she said what she said π«Ά
β¨ DESCRIPTION β¨
okay so here's the tea, bestie: this function returns the PPLL (that's Pixel PLL, iykyk) that the crtc is gonna use. π
for DP monitors, a single PPLL can be used for all DP crtcs/encoders β one PLL serving the whole group chat, very efficient, we love to see it. for non-DP monitors though? nope. a dedicated PPLL must be used. no sharing, no borrowing, everyone gets their own. π
and if a particular board has an external DP PLL, she returns ATOM_PPLL_INVALID to skip PLL programming β because there's literally no need to program the PLL itself. why do the work when the board already did it, right? π
and lastly, if we are not able to allocate a PLL, she also returns ATOM_PPLL_INVALID to skip PLL programming β and that's on purpose, to avoid messing up an existing monitor. protective queen. we stan. π
β Asic specific PLL information β
π₯ DCE 10.x Tonga π₯
- PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) CI
- PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
like, look at PPLL0 joining the party in the second one. main character energy fr fr π
π SEE ALSO π
the whole friend group, in this exact order, no cap:
Kernel file ./drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
dce_v10_0_page_flip(9)dce_v10_0_hpd_sense(9)dce_v10_0_hpd_set_polarity(9)dce_v10_0_hpd_init(9)dce_v10_0_hpd_fini(9)dce_v10_0_line_buffer_adjust(9)cik_get_number_of_dram_channels(9)dce_v10_0_dram_bandwidth(9)dce_v10_0_dram_bandwidth_for_display(9)dce_v10_0_data_return_bandwidth(9)dce_v10_0_dmif_request_bandwidth(9)dce_v10_0_available_bandwidth(9)dce_v10_0_average_bandwidth(9)dce_v10_0_latency_watermark(9)dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(9)dce_v10_0_average_bandwidth_vs_available_bandwidth(9)dce_v10_0_check_latency_hiding(9)dce_v10_0_program_watermarks(9)dce_v10_0_bandwidth_update(9)
ok that's the page!! π this lil masterpiece lives in ./drivers/gpu/drm/amd/amdgpu and it's dated October 2026 β yes, the future, because she's ahead of her time. bye bestie, go allocate some PLLs responsibly π§ββοΈπ
π¦ where this page comes from
- nixpkgs unstable: linux-manual 7.3.1
- π girlified by deepseek-ai/DeepSeek-V4.1-Flash-1017 on : a language model's rewrite of the original, under its terms