dce_v10_0_pick_pll(9)

πŸ“¦ version 7.3.1, in nixpkgs unstable

πŸ’… dce_v10_0_pick_pll(9) β€” like, the Kernel API Manual one, bestie

okay so picture this: it's a Kernel API Manual page, the star of the show is dce_v10_0_pick_pll, and she is literally the girl who hands out PPLLs to crtcs. group chat, but make it DRM. let's go ✨


🌸 NAME 🌸

dce_v10_0_pick_pll β€” allocate a PPLL for use by the crtc. that's it. that's the whole job. icon behavior honestly πŸ‘‘


πŸŽ€ SYNOPSIS πŸŽ€

u32 dce_v10_0_pick_pll (struct drm_crtc *crtc );

she takes one thing and gives you back a u32. simple. elegant. slay πŸ’…


πŸ¦‹ ARGUMENTS πŸ¦‹

  • crtc β€” a drm crtc. that's the whole description, no notes, she said what she said 🫢

✨ DESCRIPTION ✨

okay so here's the tea, bestie: this function returns the PPLL (that's Pixel PLL, iykyk) that the crtc is gonna use. πŸŽ€

for DP monitors, a single PPLL can be used for all DP crtcs/encoders β€” one PLL serving the whole group chat, very efficient, we love to see it. for non-DP monitors though? nope. a dedicated PPLL must be used. no sharing, no borrowing, everyone gets their own. πŸ™ˆ

and if a particular board has an external DP PLL, she returns ATOM_PPLL_INVALID to skip PLL programming β€” because there's literally no need to program the PLL itself. why do the work when the board already did it, right? πŸ’€

and lastly, if we are not able to allocate a PLL, she also returns ATOM_PPLL_INVALID to skip PLL programming β€” and that's on purpose, to avoid messing up an existing monitor. protective queen. we stan. πŸ‘‘

⭐ Asic specific PLL information ⭐

πŸ”₯ DCE 10.x Tonga πŸ”₯

  • PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) CI
  • PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC

like, look at PPLL0 joining the party in the second one. main character energy fr fr 🌈


🌟 SEE ALSO 🌟

the whole friend group, in this exact order, no cap:

Kernel file ./drivers/gpu/drm/amd/amdgpu/dce_v10_0.c


ok that's the page!! πŸ’– this lil masterpiece lives in ./drivers/gpu/drm/amd/amdgpu and it's dated October 2026 β€” yes, the future, because she's ahead of her time. bye bestie, go allocate some PLLs responsibly πŸ§šβ€β™€οΈπŸ“
πŸ“¦ where this page comes from