davinci_pll_clk_register(9)

📦 version 7.3.1, in nixpkgs unstable

💅 davinci_pll_clk_register(9) — a Kernel API Manual moment

okay so picture this: it's section 9 of the Kernel API Manual, the page is literally called davinci_pll_clk_register, and it's about to make your whole PLL situation make sense. bestie, let's get into it 🫶

✨ NAME ✨

davinci_pll_clk_register — registering a PLL clock, that's the whole vibe 💫

🌸 SYNOPSIS 🌸

struct clk * davinci_pll_clk_register (struct device *dev , const struct
davinci_pll_clk_info *info , const char *parent_name , void __iomem
*base , struct regmap *cfgchip );

like, look at that signature. iconic. no notes. 👑

🎀 ARGUMENTS 🎀

  • dev — the PLL platform device, or NULL if you're feeling mysterious 🙈
  • info — the device-specific clock info, aka the lore drop for this particular clock 💖
  • parent_name — the parent clock name, every main character has an origin story
  • base — the PLL's memory region, the physical spot where the magic lives
  • cfgchip — the CFGCHIP syscon regmap for info->unlock_reg, or NULL

🦋 DESCRIPTION 🦋

so this function creates a whole series of clocks that represent the PLL. not one clock. a series. it's giving ensemble cast 🌈

Here's the chain, and yes we're keeping it exactly as written:

OSCIN > [PREDIV >] PLL > [POSTDIV >] PLLEN

Breaking down every single link, because you deserve to know:

  • OSCIN is the parent clock (on secondary PLL, may come from primary PLL) — so it can lowkey be a nepo baby of the primary PLL, and that's fine 💅
  • PREDIV and POSTDIV are optional (depends on the PLL controller) — sometimes they show up, sometimes they don't, it's a vibe check 🧚
  • PLL is the PLL output (aka PLLOUT) — the moment, the main event, the star ⭐
  • PLLEN is the bypass multiplexer — the sneaky little alternate route 🔥

💀 RETURN 💀

The PLLOUT clock, or a negative error code if things did not, in fact, slay 😭

👑 SEE ALSO 👑

Kernel file ./drivers/clk/davinci/pll.c — go read it, it's right there:

all the siblings, all equally iconic, go stan them 🫶

fr fr: cfgchip is the CFGCHIP syscon regmap for info->unlock_reg — pass NULL if that's not your situation, no cap.

and that's the page babe 💖 straight out of ./drivers/clk/davinci, dated October 2026, and you're officially a PLL clock registration girlie now. periodt. 🎀✨🦋

📦 where this page comes from