XE_REG_OPTION_MASKED(9)

💖 NAME 💖

okay so bestie, welcome to XE_REG_OPTION_MASKED(9) from the Kernel API Manual — and the vibe is literally this:

• XE_REG_OPTION_MASKED — register is "masked", with the upper 16 bits marking the written bits on the lower 16 bits. 🎀✨

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✨ SYNOPSIS ✨

XE_REG_OPTION_MASKED

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🦋 DESCRIPTION 🦋

okay so the vibe check here: this option only applies to registers explicitly marked in bspec with "Access: Masked". no cap. 🙈

Registers with this option can have write operations to specific lower bits by setting the corresponding upper bits. Other bits will not be affected. This allows register writes without needing a RMW cycle and without caching in software the register value. periodt. 💅🔥

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🌸 EXAMPLE 🌸

a write with value 0x00010001 will set bit 0 and all other bits retain their previous values. 🎀

To be used with XE_REG. XE_REG_MCR and XE_REG_INITIALIZER. iykyk. 🦋

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🌈 SEE ALSO 🌈

• Kernel file ./drivers/gpu/drm/xe/regs/xe_reg_defs.h
• XE_REG_ADDR_MAX(9)
• struct xe_reg(9)
• struct xe_reg_mcr(9)
• XE_REG_OPTION_VF(9)
• XE_REG_INITIALIZER(9)
• XE_REG(9)
• XE_REG_MCR(9)

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signing off from the source/version corner at ./drivers/gpu/drm/xe/regs, dated October 2026, on the XE_REG_OPTION_MASKED(9) page — mwah 💋✨