DSB(9)

💅 DSB 💅

okay so bestie, this is the DSB(9) page from the Kernel API Manual, and we are talking about the Display State Buffer — yes, that's what DSB stands for 💖

A DSB is a queue of MMIO instructions in the memory which can be offloaded to DSB HW in the Display Controller. It's giving very "batch it and go" energy ✨

DSB HW is a DMA engine that can be programmed to download the DSB from memory. It allows the driver to batch submit display HW programming. This helps reduce loading time and CPU activity, thereby making the context switch faster. Slay, honestly 👑

DSB Support added from Gen12 Intel graphics based platform, so that's the era, iykyk 🌸

🧚 access vibe check

DSB's can access only the pipe, plane, and transcoder Data Island Packet registers. That's the whole guest list, bestie — no plus-ones 💅

DSB HW can support only register writes (both indexed and direct MMIO writes). There are no registers reads possible with DSB HW engine. Not a single read, not even a little peek 😭

👀 SEE ALSO 👀

• Kernel file ./drivers/gpu/drm/i915/display/intel_dsb.c
• intel_dsb_reg_write_indexed(9), intel_dsb_commit(9), intel_dsb_prepare(9), intel_dsb_cleanup(9)

and that's the page, bestie 🫶 it comes from ./drivers/gpu/drm/i915/display, dated October 2026, and it's DSB(9) — periodt 💖✨