VST(5)

✨ VST — the vst page, bestie edition ✨

okay so welcome to vst, aka the VHDL structural subset 💅 this is a section-5 (file formats / conventions) page, and it's giving very specific. grab a boba, we're doing structural VHDL 🧋

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🌸 ORIGIN 🌸

This software belongs to the ALLIANCE CAD SYSTEM, developed by the ASIM team at the LIP6 laboratory of Université Pierre et Marie CURIE, in Paris, France 🇫🇷🫶

• Web: http://asim.lip6.fr/recherche/alliance/
• E-mail: alliance-users@asim.lip6.fr

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💖 DESCRIPTION 💖

This document describes the ALLIANCE VHDL subset for structural descriptions. no cap, that's the whole vibe.

The declaration part of a structural description includes signal declarations and component declarations.

An internal signal can be declared of any type supported by the present VHDL subset except reg_bit and reg_vector. 🚫 those two are not invited to the party.

A component must be declared with exactly the same port description as in its entity specification. what does that mean bestie? it means local ports are to be declared with the same name, the same type, the same kind, and in the same order. same energy, same order, no exceptions 🔥

A structural description is a set of component instantiation statements. Instances' ports are connected to each other through signals in a port map specification. Both explicit and implicit port map specifications are supported by the ALLIANCE VHDL subset 👑

⚠️ heads up: the present version of the VHDL compiler does not allow unconnected ports — the open mode is not supported. 🙈

Only the concatenation operator (&) can be used in the actual part (the effective signal connected to a formal port) of a port map specification. that's the only operator invited. periodt.

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🌈 EXAMPLES 🌈

Here is the description of an adder with an accumulator register. iconic honestly.

entity add_accu is
port (
  clk      : in  bit;
  command  : in  bit;
  data_in  : in  bit_vector (31 downto 0);
  data_out : out bit_vector (31 downto 0);
  cry_out  : out bit;
  vdd      : in  bit;
  vss      : in  bit
  );
end add_accu;

architecture structural of add_accu is

signal eff_data  : bit_vector (31 downto 0);      -- effective operande
signal adder_out : bit_vector (31 downto 0);      -- adder's result
signal accu_out  : bit_vector (31 downto 0);      -- accumulator

component adder
port (a   : in  bit_vector (31 downto 0);
      b   : in  bit_vector (31 downto 0);
      res : out bit_vector (31 downto 0));
end component;

component and_32
port (a   : in  bit_vector (31 downto 0);
      cmd : in  bit;
      res : out bit_vector (31 downto 0));
end component;

component falling_edge_reg
port (din  : in  bit_vector (31 downto 0);
      clk  : in  bit;
      dout : out bit_vector (31 downto 0));
end component;

begin

  my_adder : adder
  port map (a => eff_data, b => accu_out, res => adder_out);

  my_mux   : and_32
  port map (cmd => command, a => accu_out, res => eff_data);

  my_reg   : falling_edge_reg
  port map (din => adder_out, clk => clk, dout => accu_out);

end;

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🦋 SEE ALSO 🦋

• vhdl(5)
• vbe(5)
• asimut(1)

go read those too, they're part of the lore 💜

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🎀 BUG REPORT 🎀

This tool is under development at the ASIM department of the LIP6 laboratory. 👷♀️

We need your feedback to improve documentation and tools. fr fr, they're literally asking — send the feedback, be the main character of the changelog 🌟

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and that's the whole page, bestie!! 💖 this lil' gem came from ASIM/LIP6, dated October 1, 1997 (yes it's a 90s babe and it still eats), and it lives in the man pages as VST(5). stay slay, wire your ports correctly, and never leave one open 🫶✨🌸