DLYS(5)

✨ DLYS(5) ✨

ok bestie so this is the manual page for dlys, and it lives in the File Formats Manual section, section 5 if you're keeping track 💅. It's about the format of .dlys files. Slay. Let's get into it.

🌸 NAME 🌸

dlys — the format of .dlys files, which get read by the SCALD simulator and timing verifier 🫶

🦋 DESCRIPTION 🦋

So the SCALD simulator and timing verifier? They can take in info about the actual delays of wires in a circuit. That delay info lives in a .dlys file, and a .dlys file is just a sequence of records — one record per electrical net, no more no less, periodt.

Every record starts with the signal name for the net. And listen, this is the SCALD signal name — like, the name the user gave to the entire net — and it's not usually the name of one of the pins in the net, okay? Don't get it twisted. After the signal name comes an =, then a comma-separated list of the terminals in the net and their associated delay, and the whole list gets terminated with a semicolon. Then the end of the file? That's marked with a second semicolon. Two semicolons. Iconic.

The elements of that comma-separated list for each net look like this:

location [min:max]

where location is the full hierarchical SCALD name of the physical pin the delay is computed to, and min and max are the best-case and worst-case wire delay in nanoseconds (both of them are floating-point numbers, ngl). The assumption baked in here is that there's only a single driver per net, so all delays are computed from that driver. And if a net has multiple drivers? Then how you interpret the delays is up to the program reading the file — e.g. min delays are taken from the fastest driver, max from the slowest. Just how it is 💀

Here's an example .dlys file, bestie:

(APS )ALU STATUS BITS I1<0> =
   (APS MR 3V6 R1 1P )IN#63[ 0.3 : 0.4 ],
   (APS APS 4RI RFC RF )OUT[ 0.5 : 0.7 ];
(APS )ALU STATUS BITS I1<1> =
   (APS APS 4ALUD DCD )AN#12[ 1.4 : 1.6 ],
   (APS APS 4ALUD DCD )AN#8[ 1.1 : 1.3 ],
   (APS APS 4ALUD DCD )AN#9[ 1.1 : 1.3 ],
   (APS APS 4ALUD DCD )AN#10[ 1.1 : 1.3 ],
   (APS APS 4ALUD DCD )AN#11[ 1.1 : 1.3 ],
   (APS MR 3V2 R1 1P )#23[ 0.6 : 0.8 ],
   (APS MR 3V6 R1 1P )#62[ 0.3 : 0.4 ],
   (APS APS 4ALUD DCD )[ 0.4 : 0.6 ],
   (APS APS 4ALUD DCD )#1[ 0.4 : 0.6 ],
   (APS APS 4ALUD DCD )#2[ 0.4 : 0.6 ],
   (APS APS 4ALUD DCD )#3[ 0.4 : 0.6 ],
   (APS APS 4ALUD DCD )#4[ 0.7 : 0.8 ],
   (APS APS 4ALUD DCD )#5[ 0.7 : 0.8 ];
;

Okay so. Even though it is not good practice, it is possible to omit the actual pin names from the location names and only give the path to the part. The example above literally shows several cases where the final pin name is missing, so like, it happens. 🙈

Why does that even work? Because the timing verifier and simulator have the original SCALD netlist available, so they're usually able to use the signal name to figure out the net, and then use the part's path to identify which pin of the net is meant. This is accurate when a net connects to at most one pin per part. But if it connects to more than one pin per part, then there's ambiguity over which pin is meant 😭 Usually though, this ambiguity only results in a small inaccuracy, since the delay to different pins on the same part is usually similar. Also — and this is the cute part — if the delay is capacitive, the delay to all pins in a net will be the same anyway, so there's no inaccuracy at all. Vibe check passed ✨

👑 SEE ALSO 👑

• ext2dlys(1)
• ext(5)
• sim(5)

💀 BUGS 💀

• There should be some way to specify which pins are drivers and which are receivers in a net. Like, that would be so helpful bestie.
• The ability to omit pin names is dangerous. Although it usually works, it can introduce large inaccuracies when the parts are large compared to the sizes of the wires used to connect them — as might be the case on a silicon PCB. So like, be careful with that one, fr fr.

and that's the whole page, bestie!! 🎀 this was DLYS(5) from the File Formats Manual — the footer just says DLYS(5) too, no extra source or date info attached, so that's literally all we got. go forth and format your delays, you main character 🦋💖