EXT(5)

okay bestie, this is EXT(5) from the File Formats Manual and we're about to get so familiar with the .ext file format 💖 no cap, it's giving "the file Magic writes for every single cell" and it's honestly kind of iconic.

🌸 NAME 🌸

ext — the format of .ext files produced by Magic's hierarchical extractor 🦋

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✨ DESCRIPTION ✨

so. Magic's extractor makes one .ext file for every cell in a hierarchical design. if the cell is named name, the file is called name.ext. periodt.

and inside that file? three whole flavors of info, bestie:

• environmental information — scaling, timestamps, that whole vibe
• the extracted circuit that matches the mask geometry of name
• the connections between that mask geometry and the subcells of name

a .ext file is just a series of lines, and every line starts with a keyword. the keyword at the front is what tells you how to read the rest of the line. and the following set of keywords are the ones that define the environmental info 🧚

• tech techname — says the technology of name is techname, like nmos or cmos 👑
• timestamp time — says when name was last modified. time is the value Unix stores, i.e. seconds since 00:00 GMT January 1, 1970. and no, this is not the time name was extracted — it's the timestamp value stored in the .mag file. the incremental extractor compares the timestamp in each .ext file against the timestamp in each .mag file in a design, and if they differ, that cell gets re-extracted. lowkey a whole vibe check 🔥
• version version — says which version of .ext format was used to write name.ext. the current version is 5.1 ✨
• style style — says which style the cell was extracted with.
• scale rscale cscale lscale — sets the scale used to interpret resistance, capacitance, and linear dimension values in the rest of the .ext file. here's the breakdown, don't skip it:
  • every resistance value gets multiplied by rscale to give the real resistance in milliohms
  • every capacitance value gets multiplied by cscale to give the real capacitance in attofarads
  • every linear dimension (width, height, transform coordinates, etc.) gets multiplied by lscale to give the real linear dimension in centimicrons
  • and every area dimension (like transistor channel area) gets multiplied by scale*scale to give the real area in square centimicrons

at most one scale line may appear in a .ext file. if none shows up, all of rscale, cscale, and lscale default to 1 🫶

• resistclasses r1 r2 ... — sets the resistance per square for the various resistance classes that show up in the technology file. the values r1, r2, etc. are in milliohms — and bestie, they are not scaled by the value of rscale from the scale line above. each node in a .ext file has a perimeter and an area for each resistance class, and r1, r2, etc. are what convert those perimeters and areas into actual node resistances. for the full tea on how resistances get computed from perimeters and areas, see ``Magic Tutorial #8: Circuit Extraction'' 📚

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okay now the next batch of keywords defines the circuit formed by the mask info in name. this circuit is extracted independently of any subcells — its connections to subcells are handled by the keywords in the section after this one, so don't mix them up 💅

• node name R C x y type a1 p1 a2 p2 ... aN pN — defines an electrical node in name. this node gets referred to by name in later equiv lines, in connections to transistor terminals in fet lines, and in hierarchical connections or adjustments via merge or adjust. the node has a total capacitance to ground of C attofarads and a lumped resistance of R milliohms. for going back from the node name to the geometry that defines it, (x,y) is the coordinate of a point inside the node, and type is the layer that point shows up on. the values a1, p1, ... aN, pN are the area and perimeter for the material in each of the resistance classes described by the resistclasses line at the top of the .ext file; these are what compute adjusted hierarchical resistances more accurately.

NOTE: since lots of analysis tools compute transistor gate capacitance themselves from the transistor's area and perimeter, the capacitance between a node and substrate (GND!) normally does not include capacitance from transistor gates connected to that node. if the .sim file was produced by ext2sim(1), check the technology file that was used to produce the original .ext files to see whether transistor gate capacitance is included or excluded — see ``Magic Maintainer's Manual #2: The Technology File'' for the details 😭

• attr name xl yl xh yh type text — one of these lines shows up for each label ending in the character `@` that was attached to geometry in the node name. you get the location of each attribute label (xl yl xh yh) and the type of material it was attached to (type), plus the text of the label minus the trailing `@` character (text) 🎀
• equiv node1 node2 — says two node names in cell name are equivalent: node1 and node2. in a collection of node names related by equiv lines, exactly one must be defined by a node line like the one above ⭐
• fet type xl yl xh yh area perim sub GATE T1 T2 ... — defines a transistor in name. the kind of transistor is type, a string that comes from the technology file and is meant to have meaning to simulation programs. the coordinates of a square entirely contained in the gate region of the transistor are (xl, yl) for its lower-left and (xh, yh) for its upper-right. all four coordinates are in name's coordinate space, and they're subject to scaling as described in scale above. the gate region of the transistor has area area square centimicrons and perimeter perim centimicrons. the substrate of the transistor is connected to node sub.

the rest of a fet line is a series of triples: GATE, T1, .... each one describes one of the transistor's terminals — the first describes the gate, and the rest describe the transistor's non-gate terminals (source, drain, etc.). each triple is: the name of a node connecting to that terminal, a terminal length, and an attribute list. the terminal length is in centimicrons, and it's the length of that segment of the channel perimeter connecting to adjacent material — like polysilicon for the gate, or diffusion for a source or drain.

the attribute list is either the single token `0` (meaning no attributes) or a comma-separated list of strings. those strings come from labels attached to the transistor:

• any label ending in the character `^` is considered a gate attribute and appears on the gate's attribute list, minus the trailing `^`. gate attributes may lie either along the border of a channel or in its interior 🦋
• any label ending in the character `$` is considered a non-gate attribute. it appears on the list of the terminal along which it lies, also minus the trailing `$`. non-gate attributes may only lie on the border of the channel 🙈

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the keywords in this section describe info that is not processed hierarchically: path lengths and accurate resistances that get computed by flattening an entire node and then producing a value for the flattened node 💀

• killnode node — during resistance extraction it's sometimes necessary to break a node up into several smaller nodes. a killnode line during the processing of a .ext file means that all information currently accumulated about node, along with all fets that have a terminal connected to node, should be thrown out — it'll be replaced by information later in the .ext file. the order of processing .ext files matters here: children get processed before their parents, so a killnode in a parent overrides one in a child 🔥
• resist node1 node2 R — defines a resistor of R milliohms between the two nodes node1 and node2. both names are hierarchical.
• distance name1 name2 dmin dmax — gives the distance between two electrical terminals name1 (a driver) and name2 (a receiver). note that these are terminals, not nodes — the names (which are hierarchical label names) are used to specify two different locations on the same electrical node. the two distances, dmin and dmax, are the lengths (in lambda) of the shortest and longest acyclic paths between the driver and receiver 🌸

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and this last section? it describes the subcells used by name, and how connections are made to them and between them 🧚✨

• use def use-id TRANSFORM — says that cell def with instance identifier use-id is a subcell of cell name. if cell def is arrayed, then use-id is followed by two bracketed subscript ranges of the form: [lo,hi,sep]. the first range is for x, the second for y. the subscripts for a given dimension go lo through hi inclusive, and the separation between adjacent array elements is sep centimicrons 👑

TRANSFORM is a set of six integers describing how coordinates in def get transformed to coordinates in the parent name. it's used by ext2sim(1) when transforming transistor locations to coordinates in the root of a design. the six integers of TRANSFORM (ta, tb, tc, td, te, tf) are interpreted as components in the following transformation matrix, by which all coordinates in def are post-multiplied to get coordinates in name:

                            ta   td   0
                            tb   te   0
                            tc   tf   1

Next up, the moment you've all been waiting for, the main character of this whole page:

merge path1 path2 C a1 p1 a2 p2  ... aN pN

merge is how you tell ext that two things are literally the same node, bestie. It's used to specify a connection between two subcells, or between a subcell and mask information of name. 💅

Both path1 and path2 are hierarchical node names, so let's break down how you actually write one:

• Wanna point at a node that lives in cell name itself? Then its pathname is just its node name. That's it. Simple. Iconic. ✨
• Wanna point at a node inside a subcell of name? Then your pathname is the use-id of that subcell (the exact same one it had in a use line above, no cap 🧚) + a slash (/) + the node name inside the subcell.

Concrete example so it actually sticks: if name contains subcell sub with use identifier sub-id, and sub contains node n, then the full pathname of node n relative to name is sub-id/n. 🎀

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Now, the array situation, because this part is lowkey genius. Connections between adjacent elements of an array get their own special syntax that exploits how regular arrays are. A use-id inside a path may optionally be followed by a range of the form [lo:hi] — and heads up, that goes before the following slash. A use-id like that is interpreted as elements lo through hi inclusive of a one-dimensional array. 🌈

And if you've got a two-dimensional array? An element can be subscripted with two such ranges: first the y range, then the x range. (y first, bestie, don't @ me.)

Whenever one path in a merge line contains a subscript range like that, the other one must contain one of comparable size. Like:

merge  sub-id[1:4,2:8]/a  sub-id[2:5,1:7]/b

This is acceptable because the range 1:4 is the same size as 2:5, and the range 2:8 is the same size as 1:7. Matchy matchy, slay. 💖

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Okay so here's where it gets real. When a connection happens between nodes in different cells, it may be that some resistance and capacitance got recorded redundantly. Example: polysilicon in one cell might overlap polysilicon in another, so the capacitance to substrate has been recorded twice. 😭 Not the vibe.

That's exactly what the values C, a1, p1, etc. in a merge line are for — they give you a way to compensate for that overlap:

• Each of a1, p1, etc. (usually negative, ngl) gets added to the area and perimeter for material of each resistance class, giving an adjusted area and perimeter for the aggregate node.
• The value C in attofarads (also usually negative) gets added to the sum of the capacitances (to substrate) of nodes path1 and path2 to give the capacitance of the aggregate node.

So yeah, negative numbers here are doing the work, they're not a typo. 🫶

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Then we have:

cap node1 node2 C

cap defines a capacitor between the nodes node1 and node2, with capacitance C. This construct is used to specify both internodal capacitance within a single cell and between cells. Two-for-one, we love efficiency. ⭐

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👑 AUTHOR

Walter Scott

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🔥 SEE ALSO

ext2sim(1), magic(1)

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And that's the whole page, bestie — you made it to the end, main character energy fr fr. 💜 This one comes from the 4th Berkeley Distribution, and the page itself is EXT(5). Go forth and merge responsibly, mwah. 💅✨