xgene_ahci_do_hardreset(9)

📦 version 7.3.1, in nixpkgs unstable

💅 xgene_ahci_do_hardreset — from the Kernel API Manual, bestie 🎀

okay so picture this: it's a Kernel API Manual page, the star is xgene_ahci_do_hardreset(9), and she is literally the one who issues the actual COMRESET. no middleman. no vibe-based guessing. just PHY drama. let's get into it ✨

🌸 NAME 🌸

xgene_ahci_do_hardreset — issue the actual COMRESET 🫶

✨ SYNOPSIS ✨

int xgene_ahci_do_hardreset (struct ata_link *link , unsigned long
deadline , bool *online );

🦋 ARGUMENTS 🦋

  • link — the link you're resetting, bestie. that's the whole assignment.
  • deadline — the deadline in jiffies for the operation. she has a clock and she's watching it ⏰
  • online — a return value that tells you whether the device is online. yes, it's a return value that comes back through a pointer. iconic behavior, we respect it 💅

👑 DESCRIPTION 👑

so here's the tea ☕ — the hardware PHY has limitations, and because of that, each supported disk speed needs a different set of settings:

  • Gen3 (6.0Gbps)
  • Gen2 (3.0Gbps)
  • Gen1 (1.5Gbps)

if you don't do that? during a long IO stress test the PHY will report disparity error and etc. and etc. is doing a LOT of heavy lifting in that sentence 😭

also, during COMRESET there can be errors reported in the register PORT_SCR_ERR. for SERR_DISPARITY and SERR_10B_8B_ERR, the PHY receiver line must be reseted. (that's the manpage's spelling and I'm keeping it, no cap 🫶)

and here's the other thing — during long reboot cycle regression, sometimes the PHY reports link down even if the device is present, because of speed negotiation failure. so you gotta retry the COMRESET to get the link up. lowkey rude of the PHY but okay.

the following algorithm is followed to proper configure the hardware PHY during COMRESET:

⭐ Alg Part 1 ⭐

  1. Start the PHY at Gen3 speed (default setting)
  2. Issue the COMRESET
  3. If no link, go to Alg Part 3
  4. If link up, determine if the negotiated speed matches the PHY configured speed
  5. If they matched, go to Alg Part 2
  6. If they do not matched and first time, configure the PHY for the linked up disk speed and repeat step 2
  7. Go to Alg Part 2

💖 Alg Part 2 💖

  1. On link up, if there are any SERR_DISPARITY and SERR_10B_8B_ERR error reported in the register PORT_SCR_ERR, then reset the PHY receiver line
  2. Go to Alg Part 4

🌈 Alg Part 3 🌈

  1. Check the PORT_SCR_STAT to see whether device presence detected but PHY communication establishment failed and maximum link down attempts are less than Max attempts 3 then goto Alg Part 1.
  2. Go to Alg Part 4.

🍓 Alg Part 4 🍓

  1. Clear any pending from register PORT_SCR_ERR.

🎀 NOTE 🎀

for the initial version, we will NOT support Gen1/Gen2. periodt. 🙈

in addition — and until the underlying PHY supports an method to reset the receiver line — on detection of SERR_DISPARITY or SERR_10B_8B_ERR errors, an warning message will be printed. she's not fixing it, she's announcing it. main character energy honestly 💀

🔥 SEE ALSO 🔥

kernel file ./drivers/ata/ahci_xgene.c plus the whole friend group:

and that's the page!! brought to you by the source at ./drivers/ata, dated October 2026, filed under the Kernel API Manual — go read the whole crew, they all ate 💜✨

📦 where this page comes from