xe_device_td_flush(9)

📦 version 7.3.1, in nixpkgs unstable

💅 xe_device_td_flush(9) — a Kernel API Manual moment

okay so this is xe_device_td_flush, bestie, and it's living in the kernel API manual. sit down, we're learning about cache flushing 🫶

✨ NAME ✨

xe_device_td_flush — flushes out those transient L3 cache entries, no cap 💖

🌸 SYNOPSIS 🌸

void xe_device_td_flush (struct xe_device *xe );

🎀 ARGUMENTS 🎀

  • xe — the device. that's it, that's the argument, she's a simple queen 👑

🦋 DESCRIPTION 🦋

okay so picture this: the display engine has direct access to memory, right? and it is never coherent with the L3/L4 caches (or the CPU caches either, ngl they're not on speaking terms 💀). but here's the thing — KMD</> is the one responsible for specifically flushing those transient L3 GPU cache entries before the flip sequence happens, so that scanout can actually happen from a surface like that without seeing corruption. like, the whole point is no corruption. periodt. 🔥

and how do surfaces get tagged as transient in the first place? you map them using one of the various L3:XD PAT index modes on Xe2. that's the vibe check ✅

💀 NOTE 💀

listen, on non-discrete xe2 platforms — like LNL, for example — the entire L3 cache gets flushed at the end of every single submission via PIPE_CONTROL for compute/render. why? because SA Media is not coherent with L3 and we want to support render-vs-media use cases, obviously 🧚

and for the other engines, like copy/blt? the HW internally forces uncached behaviour. that's literally why we can skip the TDF on those platforms. iykyk 💅

⭐ SEE ALSO ⭐

kernel file ./drivers/gpu/drm/xe/xe_device.c, plus the whole friend group:

and that's the page, bestie 💖✨ this icon of a manpage lives in ./drivers/gpu/drm/xe, dated October 2026, and it's still xe_device_td_flush(9) at the end of the day. slay 🎀🦋

📦 where this page comes from