TILING SWIZZLING DETAILS(9)

✨ tiling swizzling details(9) — Kernel API Manual ✨

okay so bestie 💖 the whole idea behind tiling is to increase cache hit rates by rearranging pixel data so that a group of pixel accesses are in the same cacheline. The performance improvement from doing this on the back/depth buffer is on the order of 30%. periodt. 💅

Intel architectures make this somewhat more complicated, though, by adjustments made to addressing of data when the memory is in interleaved mode (matched pairs of DIMMS) to improve memory bandwidth. 🌈 For interleaved memory, the CPU sends every sequential 64 bytes to an alternate memory channel so it can get the bandwidth from both. no cap.

The GPU also rearranges its accesses for increased bandwidth to interleaved memory, and it matches what the CPU does for non-tiled. 🦋 However, when tiled it does it a little differently, since one walks addresses not just in the X direction but also Y. So, along with alternating channels when bit 6 of the address flips, it also alternates when other bits flip -- Bits 9 (every 512 bytes, an X tile scanline) and 10 (every two X tile scanlines) are common to both the 915 and 965-class hardware. 😭 this is so specific and I love it.

The CPU also sometimes XORs in higher bits as well, to improve bandwidth doing strided access like we do so frequently in graphics. This is called "Channel XOR Randomization" in the MCH documentation. The result is that the CPU is XORing in either bit 11 or bit 17 to bit 6 of its address decode. 👑

All of this bit 6 XORing has an effect on our memory management, as we need to make sure that the 3d driver can correctly address object contents. ✨

If we don't have interleaved memory, all tiling is safe and no swizzling is required. 💖

When bit 17 is XORed in, we simply refuse to tile at all. Bit 17 is not just a page offset, so as we page an object out and back in, individual pages in it will have different bit 17 addresses, resulting in each 64 bytes being swapped with its neighbor! 💀

Otherwise, if interleaved, we have to tell the 3d driver what the address swizzling it needs to do is, since it's writing with the CPU to the pages (bit 6 and potentially bit 11 XORed in), and the GPU is reading from the pages (bit 6, 9, and 10 XORed in), resulting in a cumulative bit swizzling required by the CPU of XORing in bit 6, 9, 10, and potentially 11, in order to match what the GPU expects. 🎀

💖 SEE ALSO 💖

• Kernel file ./drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c — fence register handling(9)
• i915_vma_revoke_fence(9)
• i915_vma_pin_fence(9)
• i915_reserve_fence(9)
• i915_unreserve_fence(9)
• intel_ggtt_restore_fences(9)
• detect_bit_6_swizzle(9)
• i915_gem_object_do_bit_17_swizzle(9)
• i915_gem_object_save_bit_17_swizzle(9)

xoxo bestie 🫶 source: ./drivers/gpu/drm/i915/gt · date/version: October 2026 · page: tiling swizzling details(9) · Kernel API Manual out 💜