tegra_dc_state_setup_clock(9)

πŸ“¦ version 7.3.1, in nixpkgs unstable

πŸ’… tegra_dc_state_setup_clock(9) πŸ’…

okay bestie so we're in the Kernel API Manual today and the main character of this whole page is tegra_dc_state_setup_clock β€” say it with me, it's giving very long function name energy but we're gonna get through it together 🫢

✨ NAME ✨

tegra_dc_state_setup_clock β€” check clock settings and store them in atomic state

like, it checks the clock settings first and then tucks them safely into the atomic state. two jobs, one function, she's booked and busy πŸ’…

πŸŽ€ SYNOPSIS πŸŽ€

int tegra_dc_state_setup_clock (struct tegra_dc *dc , struct
       drm_crtc_state *crtc_state , struct clk *clk , unsigned long pclk ,
       unsigned int div );

five arguments, no cap. she returns an int. let's meet the whole friend group 🌸

πŸ¦‹ ARGUMENTS πŸ¦‹

  • dc β€” display controller. the whole vibe, the main character of the display world πŸ‘‘
  • crtc_state β€” CRTC atomic state. this is where the clock settings get stored, bestie, it's her little locker πŸŽ€
  • clk β€” parent clock for display controller. the actual clock in question, the one getting checked ✨
  • pclk β€” pixel clock. yes her, the pixel clock, very important, very iconic πŸ’–
  • div β€” shift clock divider. the divider, shifting away, doing her thing 🧚

πŸ“ RETURN πŸ“

0 on success, or a negative error-code on failure 😭

so like, 0 = slay, negative = not slay. check it, okay? don't just assume it worked because that's how you end up confused and sad πŸ™ˆ

⭐ SEE ALSO ⭐

  • Kernel file ./drivers/gpu/drm/tegra/dc.c β€” go read the source, it's literally right there, iykyk πŸ’œ

and that's the whole page bestie, you ate that πŸ“πŸ’…

with love from ./drivers/gpu/drm/tegra, dated October 2026 β€” that's the source/version and the date, and no i'm not copying the footer line, i'm mentioning it cutely, periodt πŸŒˆπŸ‘‘

πŸ“¦ where this page comes from