STRUCT ZYNQMP_CLK_DIVIDER(9)

💅 struct zynqmp_clk_divider(9)

okay bestie, welcome to the Kernel API Manual, we're looking at struct zynqmp_clk_divider today and honestly? it's giving adjustable divider clock energy and I'm lowkey obsessed 🎀

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✨ NAME ✨

struct zynqmp_clk_divider — the adjustable divider clock struct, fr fr 💖

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🌸 SYNOPSIS 🌸

struct zynqmp_clk_divider {
    struct clk_hw hw;
    u8 flags;
    bool is_frac;
    u32 clk_id;
    u32 div_type;
    u16 max_div;
 };

no cap, that's the whole shape of it. let's break down every single member because we do NOT skip parts in this house 💅

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🦋 Members 🦋

🌈 the fields, one by one

• hw — this is the handle between the common clock interfaces and the hardware-specific ones. it's the little bridge between two worlds, main character energy honestly 🫶
• flags — hardware-specific flags. not our generic flags, hardware specific, iykyk ✨
• is_frac — a bool, and it answers one question: is this divider a fractional divider? yes or no, no in-between 💀
• clk_id — the id of the clock. that's it, that's the vibe 👑
• div_type — the divisor type. and bestie, it's literally TYPE_DIV1 or TYPE_DIV2, those are the two options, periodt 🔥
• max_div — the maximum supported divisor. and listen — it's fetched from firmware, so it's not just vibes, it's official 💖

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💜 SEE ALSO 💜

• Kernel file ./drivers/clk/zynqmp/divider.c — go read it, it's right there 🍓
• zynqmp_clk_divider_recalc_rate(9)
• zynqmp_clk_divider_determine_rate(9)
• zynqmp_clk_divider_set_rate(9)
• zynqmp_clk_get_max_divisor(9)
• zynqmp_clk_register_divider(9)

like, the whole squad is linked up there, go say hi 🌸

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heads up bestie: max_div comes from firmware — it's not something you just make up, okay? respect the firmware 🙈

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okay that's the page!! mwah 💋 this was ./drivers/clk/zynqmp, October 2026, Kernel API Manual — go forth and divide those clocks adjustably, you absolute icon 🧚✨👑